Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-03-15
2002-08-20
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S088000, C438S745000, C438S756000, C438S757000
Reexamination Certificate
active
06436833
ABSTRACT:
BACKGROUND OF THE INVENTION
(1
) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming planarized shallow trench isolation structures in the manufacture of integrated circuit devices.
(2
) Description of the Prior Art
Shallow trench isolation (STI) is now commonly used in the art as an alternative to local oxidation of silicon (LOCOS) for forming isolations between active device areas in the integrated circuit. STI offers the advantages of smaller isolation area and better surface planarization when compared to LOCOS. However, the STI process suffers from non-uniform planarization and dishing, especially over large trenches because of poor initial wafer topology. Dishing can cause excessive device leakage in some cases. Currently, reverse masking, dummy active structures, and more recently, nitride capping layers, are the most commonly employed methods to prevent dishing during the STI chemical mechanical polishing (CMP) process. However, reverse masking steps incur additional processing costs. Dummy structures, on the other hand, cause an increase in parasitic capacitance that is not favorable, especially in mixed signal processes. These processes are expensive and time-consuming.
Co-pending U.S. patent applications Ser. No. 09/439,357 to James Lee, filed on Nov. 11, 1999 now U.S. Pat. No. 6,197,691 issued on Mar. 6, 2001, and Ser. No. 09/803,187 to V. S. K. Lim et al, filed on Mar. 12, 2001 now Allowed, teach nitride capping techniques for preventing dishing in an STI process using HDP-CVD oxide. Several prior art approaches disclose methods to form and planarize shallow trench isolations. U.S. Pat. No. 5,173,439 to Dash et al teaches an STI process using a polysilicon layer to shield the oxide in wide trenches, etching away the oxide not covered by the polysilicon, and finally a CMP of the polysilicon and remaining oxide. U.S. Pat. No. 5,880,007 to Varian et al teaches a polysilicon layer over HDP oxide within trenches. CMP exposes the oxide, then the polysilicon and oxide are etched separately followed by an oxide CMP. U.S. Pat. No. 6,048,775 to Yao et al shows a process in which a silicon nitride capping layer is used. U.S. Pat. No. 5,721,173 to Yano et al uses a polysilicon capping process in which the polysilicon is subjected to CMP, the oxide not covered by the polysilicon is etched away, and the remaining polysilicon is polished by CMP. U.S. Pat. No. 6,001,706 to Tan et al and U.S. Pat. No. 6,107,159 to Chuang show other STI methods.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating shallow trench isolations in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate shallow trench isolations where oxide dishing is eliminated.
Another object of the present invention is to provide a method to fabricate shallow trench isolations having better planarity control.
Yet another object of the invention is to provide a method to fabricate shallow trench isolations wherein oxide dishing is eliminated and better planarity control is achieved.
In accordance with the objects of this invention, a new method of forming shallow trench isolations has been achieved. An etch stop layer is deposited on the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the etch stop layer into the semiconductor substrate to separate active areas. An oxide layer is deposited over the etch stop layer and within the isolation trenches wherein the oxide fills the isolation trenches and overlies the etch stop layer on the active areas. A polysilicon layer is deposited overlying the oxide layer within the isolation trenches and the oxide layer overlying the etch stop layer. The polysilicon layer is polished away until the oxide layer overlying the etch stop layer is exposed and the polysilicon layer remains only overlying the oxide layer in the isolation trenches. The polysilicon layer is oxidized whereby the oxidized polysilicon layer has a height close to the height of the oxide layer overlying the etch stop layer. The oxidized polysilicon layer, the oxide layer overlying the etch stop layer, and the oxide layer in the isolation trenches is polished down until the etch stop layer is reached thereby planarizing the isolation trenches to complete planarized shallow trench isolation regions in the manufacture of an integrated circuit device.
REFERENCES:
patent: 5173439 (1992-12-01), Dash et al.
patent: 5721173 (1998-02-01), Yano et al.
patent: 5880007 (1999-03-01), Variam et al.
patent: 6001706 (1999-12-01), Tan et al.
patent: 6048775 (2000-04-01), Yao et al.
patent: 6107159 (2000-08-01), Chuang
Feng Chen
Hing Peter
Pang Chong Hau
See Alex
Ackerman Stephen B.
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Powell William A.
Saile George O.
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