Method for positioning bond pads in a semiconductor die layout

Details Method for positioning bond pads in a semiconductor die layout Method for positioning bond pads in a semiconductor die layout

1994-10-11

1996-03-12

Fourson, George

Fishing, trapping, and vermin destroying

437204, H01L 2128, H01L 2160

Patent

active

054987679

ABSTRACT:
A process for positioning bond pads around a semiconductor die periphery on an octant basis, taking into account both manufacturing and design limitations. The process positions bond pad centers such that the spacing (pitch) increases towards the die corners. The pitch increase is iteratively calculated from an approximated wire angle. The process iteratively recalculates an octant's pad positions until optimum values are converged upon for the approximated wire angle of the cornermost bond pad and for the furthest allowable position for the cornermost bond pad. Once these optimum values are achieved, the resulting bond pad coordinates are stored in memory or a storage media in a format readable by a layout tool being used to design the die (or package). The resulting file is imported into the layout tool, which uses the stored information to physically position bond pads around the die periphery in the die layout.

REFERENCES:
patent: 5155065 (1992-10-01), Schweiss
patent: 5245214 (1993-09-01), Simpson
W. E. Jahsman; "Lead Frame and Wire Length Limitations to Bond Densification;" Journal of Electronic Packaging; vol. 111, pp. 289-293 (Dec. 1989).
W. Huddleston, et al.; "I.C. Package Inner Lead and Chip Bond Pad Layout Recommendations for Robust . . . " International Elec. Pkg. Conf. Sep. 12-15, '93; vol. 1, pp. 694-702 (1993).
User's Manual for K&S Process Support Tools-Fine Pitch Model by Kulicke & Soffa Industries Inc.; (1993).

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