Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1990-10-29
1991-11-12
Beck, Shrive
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
4272552, 4272557, 427355, 51281R, 51310, B05D 306
Patent
active
050646834
ABSTRACT:
In a polish palnarization process using a polishing apparatus and an abrasive slurry, a boron nitride (BN) polish stop layer (18) is provided to increase the polish selectivity. The BN layer deposited in accordance with the invention has a hexagonal-close-pack crystal orientation and is characterized by chemical inertness and high hardness. The BN layer has a negligible polish removal rate yielding extremely high polish selectivity when used as a polish stop for polishing a number of materials commonly used in the fabrication of semiconductor devices. In accordance with the invention, a substrate (12) is provided having an uneven topography including elevated regions and recessed regions. A BN polish stop layer (18) is desposited to overlie the substrate (12) and a fill material (20, 36) which can be dielectric material or a conductive material, is deposited to overlie the BN polish stop (18) and the recessed regions of the substrate. The fill material is then polished back until the BN polish stop is reached resulting in the formation of a planar surface (38).
REFERENCES:
patent: 4627991 (1986-12-01), Seki et al.
patent: 4671851 (1987-06-01), Beyer et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4910155 (1990-03-01), Cote et al.
patent: 4944836 (1990-07-01), Beyer et al.
"Properties of the B-Si-N Ceramic Thin Films by Plasma-CVD" Takahiro Nakahigashi et al., Shinku (Vacuum), vol. 31, No. 9, pp. 789-795 (1988) Translation provided.
Gelatos Avgerinos V.
Poon Stephen S.
Beck Shrive
Dockrey Jasper W.
King Robert L.
Motorola Inc.
Utech Benjamin L.
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