Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
1998-11-23
2001-05-15
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C310S366000, C347S068000, C347S071000, C347S072000
Reexamination Certificate
active
06232132
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method for polarization treatment of a piezoelectric/electrostrictive film type chip which is integrated piezoelectric/electrostrictive film type elements.
(2) Description of Prior Art
In recent years, there has been known, as a mechanism for increasing the pressure inside a pressure room formed in a material, a piezoelectric/electrostrictive film type element which is fixed on the wall of the pressure room and which can change the volume of the pressure room owing to the displacement of the piezoelectric/electrostrictive section. Such a piezoelectric/electrostrictive film type element is being used, for example, as the ink pump of a print head used in an ink jet printer.
The print head is formed by integrating a plurality of piezoelectric/electrostrictive film type elements to produce an piezoelectric/electrostrictive film type chip and joining the chip with an ink nozzle member. Prior to the joining, the piezoelectric/electrostrictive film type chip is generally subjected to a polarization treatment to polarize it to a given direction.
FIG. 2
is a sectional view showing part of a piezoelectric/electrostrictive film type element. On a diaphragm
10
are laminated a lower electrode
11
, a piezoelectric/electrostrictive layer
12
and an upper electrode
13
in this order, whereby a piezoelectric/electrostrictive film type element
15
is constituted. Such a piezoelectric/electrostrictive film type element
15
is integrated by, for example, 66 elements, whereby a piezoelectric/electrostrictive film type chip
20
as shown in
FIG. 3
is formed. In the piezoelectric/electrostrictive film type chip
20
, the piezoelectric/electrostrictive layers
12
of the piezoelectric/electrostrictive film type elements
15
are formed each independently, but the upper electrodes
13
and the lower electrodes
11
are respectively connected between the piezoelectric/electrostrictive film type elements
15
.
The polarization treatment to such a piezoelectric/electrostrictive film type chip
20
has been conducted by, as shown in
FIG. 3
, forming a circuit
22
for polarization treatment between the upper electrodes
13
and the lower electrodes
11
of the piezoelectric/electrostrictive film type elements
15
and applying a given voltage to the circuit. In
FIG. 3
, R is a load resistance used in the circuit
22
for polarization treatment, and
23
is an electric source.
When the piezoelectric/electrostrictive film type chip
20
is subjected to a polarization treatment as above, however, dielectric breakdown arises in the chip
20
when the piezoelectric/electrostrictive layer
12
has defects. When the defects are large and the dielectric breakdown is high, those piezoelectric/electrostrictive film type elements having such defects become unusable. A study by the present inventor indicated that when the dielectric breakdown is low, the piezoelectric/electrostrictive film type elements showing such dielectric breakdown are hardly affected in the performance and are sufficiently usable as piezoelectric/electrostrictive film type elements.
SUMMARY OF THE INVENTION
The present invention has been completed based on the above finding. The object of the present invention is to provide a method for polarization treatment of a piezoelectric/electrostrictive film type chip, wherein the chip comprising a plurality of piezoelectric/electrostrictive film type elements is divided into two or more element groups and each group is subjected to a polarization treatment, thereby allowing the elements to have low dielectric breakdown and be usable as reliable elements.
According to the present invention, there is provided a method for polarization treatment of a piezoelectric/electrostrictive film type chip, comprising:
providing a piezoelectric/electrostrictive film type chip comprising a plurality of piezoelectric/electrostrictive film type elements each having a piezoelectric/electrostrictive section constituted by a thin diaphragm, a lower electrode formed on the diaphragm, a piezoelectric/electrostrictive layer formed on the lower electrode, and an upper electrode formed on the piezoelectric/electrostrictive layer,
dividing the plurality of piezoelectric/electrostrictive film type elements into two or more element groups, and
subjecting each element group to a polarization treatment.
In the above method, it is preferred that a circuit for polarization treatment is formed for each element group so as to contain a resistance R which is set to be smaller than the insulation resistance of the element group and larger than the resistance of the element group when short-circuiting takes place. The resistance R is preferably not larger than {fraction (1/10)} of the insulation resistance of the element group and at least 10 times the resistance of the element group when short-circuiting takes place; the resistance R is more preferably {fraction (1/10)} to {fraction (1/100)} of the insulation resistance of the element group and 10 to 100 times the resistance of the element group when short-circuiting takes place.
REFERENCES:
patent: 4340786 (1982-07-01), Tester
patent: 4612145 (1986-09-01), Keith et al.
patent: 5266964 (1993-11-01), Takahashi et al.
Patent Abstracts of Japan, vol. 1997, No. 10, Oct. 31, 1997 & JP 09 148647 A (Toyota Motor Corp.), Jun. 6, 1997.
Patent Abstracts of Japan, vol. 010, No. 367 (E-462), Dec. 9, 1986 & JP 61 161779 A (Toshiba Ceramics Co. Ltd.), Jul. 22, 1986.
Komazawa Masato
Mizutani Toshihisa
Yano Shinsuke
Bowers Charles
Burr & Brown
Lee Hsien-Ming
NGK Insulators Ltd.
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