Method for plating using nested plating buses and semiconductor

Details Method for plating using nested plating buses and semiconductor Method for plating using nested plating buses and semiconductor

1993-10-18

1995-11-14

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361772, 361777, 174261, H05K 702

Patent

active

054672520

ABSTRACT:
Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

REFERENCES:
patent: 4989317 (1991-02-01), Firl et al.
patent: 5126813 (1992-06-01), Takahashi et al.
patent: 5218172 (1993-06-01), Seidel

Affiliated with

Also associated with

Rating

Method for plating using nested plating buses and semiconductor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for plating using nested plating buses and semiconductor , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for plating using nested plating buses and semiconductor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1225330