Method for plating using nested plating buses and semiconductor

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

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361772, 361777, 174261, H05K 702

Patent

active

054672520

ABSTRACT:
Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

REFERENCES:
patent: 4989317 (1991-02-01), Firl et al.
patent: 5126813 (1992-06-01), Takahashi et al.
patent: 5218172 (1993-06-01), Seidel

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