Method for plating using nested plating buses and semiconductor

Details Method for plating using nested plating buses and semiconductor Method for plating using nested plating buses and semiconductor

1997-11-14

2000-07-11

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361748, 361761, 361772, 361775, 361776, 361777, 257692, 257784, 257697, 257690, 257787, 257778, 257741, 174261, 174 70B, 29840, H05K 702

Patent

active

RE0367737

ABSTRACT:
Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

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