Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Patent
1998-04-02
2000-10-17
Gorgos, Kathryn
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
205135, C25D 502
Patent
active
061325880
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL BACKGROUND OF THE INVENTION
This invention relates to a process for forming a deposit layer on an isolated conductor circuit pattern of wiring circuit boards employed in the field of electronic material.
DISCLOSURE OF PRIOR ART
In recent years, technology has rapidly progressed in dimensional minimization of electronic equipment, however there still exists an increased demand for a higher mounting density Additionally there is demand for a process to form a fine isolated conductor circuit pattern of a wiring circuit board and further a need for a method of forming a deposit coat layer on only a part of the fine isolated conductor circuit pattern.
In forming the bumps, it has been generally known that, for example, other portions than the desired bump forming portions are coated with a resist to the plating, thereafter an electroplating is performed, and then the resist is peeled off to obtain the bumps.
In the case of forming the bumps in the wiring circuit board having the fine and isolated conductor pattern by means of the conventional electroplating process, however, it has been required to have a dummy conductor circuit pattern for a power supply to the bump forming portions, and there have been such defects that the necessary conductor circuit pattern is subjected to a side etching to cause a risk of wire breakage to arise upon etching-removal of the dummy conductor circuit pattern after the bump formation or, in an event where such metal as Sn is used for forming the bumps, there is a risk that Sn itself is excessively damaged upon etching off the dummy conductor circuit pattern.
DESCRIPTION OF THE INVENTION
present invention has been suggested to overcome the foregoing problems, and its object is to provide a process of plating on isolated conductor circuit, which process being capable of forming a metal deposit coat at desired positions on the isolated conductor circuit pattern without giving to the necessary conductor circuit pattern any damage, in the wiring circuit board having the fine and isolated conductor circuit pattern.
In order to establish the foregoing object, the process of plating on the isolated circuit in an optimum embodiment of the present invention is a process of plating on the isolated conductor circuit pattern of the wiring circuit board through the electroplating, characterized in comprising the steps of forming on the wiring circuit board an electrically conducting layer with a material electrically conductive and peelable with any one of heat, solvent and alkali, so as to be at least in contact with the isolated conductor circuit pattern requiring the formation of the deposit coat, forming a protect layer such as a peelable plating resist layer at least at other portions than those requiring the formation of the deposit coat and to be superposed on the electrically conducting layer, depositing a metal at the portions where the protect layer is not formed through an electroplating with the electrically conducting layer used as a power supply layer, and peeling off the electrically conducting layer and protect layer left on the wiring circuit board.
In this case, it is possible to form the deposit coat on the isolated conductor circuit pattern through the electroplating while supplying the power through the electrically conducting layer without employing the conventional dummy conductor circuit, and further the electrically conducting layer can be peeled off by means of heat, solvent or alkali, without requiring any etching by means of such strong acid or the like as required for the conventional dummy conductor, so that the required conductor circuit pattern can be prevented from being damaged, and the desired deposit coat can be stably formed.
Other objects and advantages of the present invention shall be made clear in the following description detailed with reference to embodiments shown in accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1(a) to 1(d) show in sectioned views respective steps of plating on the isolated circuit in an embodim
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Kawahara Tomoyuki
Takahashi Hiroaki
Yoshizawa Izuru
Gorgos Kathryn
Matsushita Electric & Works Ltd.
Smith-Hicks Erica
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