Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
2000-10-27
2003-02-11
Talbot, Brian K. (Department: 1762)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C205S123000, C205S125000, C205S126000, C205S183000, C438S643000, C438S668000, C438S672000, C438S674000, C438S687000
Reexamination Certificate
active
06517894
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a substrate plating method and apparatus, and particularly to a substrate plating apparatus for filling pits for fine wires and the like formed in a semiconductor wafer with copper or another metal.
BACKGROUND ART
Conventionally, wire channels have been formed in a semiconductor wafer by first depositing a conducting layer on the wafer surface using sputtering or a similar technique. Next, the unnecessary portions of the conducting layer are removed through a chemical dry etching process with a pattern mask formed of resist or the like.
In conventional processes, aluminum (Al) or an aluminum alloy has been used to form the wire circuit. However, wiring has been made thinner to keep up with the increased complexity of semiconductor devices. The increasing current density generates increased thermal stress and higher temperatures. This causes stress-migration or electro-migration, which grow more remarkable as the layers of aluminum or the like are manufactured thinner and give rise to such disorders as wire breakage or short-circuiting.
To avoid an excessive generation of heat in the wiring, a metal having a higher conductivity such as copper is required to form the wiring. However, it is difficult to perform dry etching on copper or a copper alloy that has been deposited over the entire surface as in the process described above. An alternative process would be to first form channels for the wiring according to a predetermined pattern and then fill the channels with copper or a copper alloy. This method eliminates the process of removing unnecessary parts of the conductive layer by etching, requiring only that the surface of the wafer be polished to remove uneven areas. The method has the additional benefit of being able to form simultaneously multiple areas called plugs that connect the tops and bottoms of channels.
However, the shape of these wiring channels and plugs have a considerably high aspect ratio (the ratio of depth to width) as the width of the wiring gets smaller, making it difficult to fill the channels with an even layer of metal using sputtering In deposition. The chemical vapor deposition method (CVD) has been used for depositing various materials, but it is difficult to prepare an appropriate gas material for copper or a copper alloy. Further, when using an organic material, carbon from the material becomes mixed in with the deposition layer and increases the resistance.
Therefore, a method was proposed for performing electroless or electrolytic plating by immersing a substrate into a plating solution. With this method, it is possible to fill wire channels having a high aspect ratio with a uniform layer of metal.
When performing an electrolytic plating process, for example, generally a plating solution having a composition including copper sulfate and sulfuric acid is used. If the solution has a low concentration of copper sulfate and a high concentration of sulfuric acid, it is known that the plating solution will have high conductivity and great polarization, thereby improving throwing power and coating uniformity. In contrast, if the plating solution has a high concentration of copper sulfate and a low concentration of sulfuric acid, it is known that through the work of an additive the solution will have good leveling ability, in other words, plating will grow from the bottom of the fine pits formed in the substrate surface.
For this reason, performing a plating process using a plating solution having a composition superior in throwing power and coating uniformity to fill copper in the fine pits of a substrate having a large aspect ratio, the leveling ability of the solution is poor. The inlets of the fine pits will be blocked first before the pits are filled, thereby tending to form voids in the pits. On the other hand, using a plating solution with a composition superior in leveling ability will be inferior in throwing power and coating uniformity, resulting in unplated areas on the walls and bottoms of the fine pits.
Generally in these plating processes, a copper seed layer is formed on the bottom surface and area surrounding the fine pits of the substrate. However, when performing electrolytic plating directly on a barrier layer, such as TiN or TaN, the sheet resistance of the barrier layer is much larger than the resistance of the copper sulfate plating solution. As a result, needle-shaped crystals are formed in plating processes using copper sulfate solution, resulting in a plating layer having loose adherence.
In addition a copper pyrophosphate plating solution is also widely used because of its close adhesion due to high polarization and layered deposition property. However, copper pyrophosphate plating solution has poor leveling ability. Hence, when filling fine pits with copper in a plating process using copper pyrophosphate plating solution, the inlets to the fine pits become blocked first, thereby developing voids, as described above. Of course, it is also possible to use copper pyrophosphate plating solution as a first layer over a copper seed layer.
DISCLOSURE OF INVENTION
In view of the foregoing, it is an object of the present invention to provide a method and apparatus of plating a substrate capable of filling fine pits of channels and the like for fine wiring with copper, a copper alloy, or similar material having a low electrical resistance, such that the plating is uniform with no gaps and has a smooth surface.
These objects and others will be attained by a method for plating a substrate having a surface with fine pits formed therein, the method comprising; performing a first plating process by immersing the substrate in a first plating solution having a composition superior in throwing power; and performing a second plating process by immersing the substrate in a second plating solution having a composition superior in leveling ability.
With this method, a uniform initial plating layer without unplated areas on the side walls and bottom of the fine pits is formed in the first plating process. A surface plating layer having a smooth surface and no void is formed on top of the initial plating layer in the second plating process.
According to another aspect of the present invention, the first plating solution is a high throwing power copper sulfate plating solution for printed circuit boards and the second plating solution is a copper sulfate solution. The high throwing power copper sulfate plating solution has a low concentration of copper sulfate, a high concentration of sulfuric acid, and is therefore superior in throwing power and coating uniformity. The copper sulfate plating solution has a high concentration of copper sulfate and a low concentration of sulfuric acid and is superior in leveling ability. As a result, plating metal is uniformly deposited on the surface of the semiconductor wafer, eliminating unplated areas formed on the side and bottom surfaces of the fine pits.
According to another aspect of the present invention, the high throwing power copper sulfate plating solution has a composition of 5-100 g/l of copper sulfate and 100-250 g/l of sulfuric acid, and the copper sulfate solution has a composition of 100-300 g/l of copper sulfate and 10-100 g/l of sulfuric acid.
According to another aspect of the present invention, a method for plating a substrate having a surface with fine pits formed therein and coated with a barrier layer, comprises; performing a first plating process by immersing the substrate in a first plating solution having a composition superior in throwing power and in closely adhering to the barrier layer; and performing a second plating process by immersing the substrate in a second plating solution having a composition superior in leveling ability.
With this method, a uniform initial plating layer without unplated areas on the side walls and bottom of the fine pits covered by the barrier layer is formed in the first plating process. A surface plating layer having a smooth surface and no void is formed on top of the initial plating layer in the second plat
Hongo Akihisa
Kimizuka Ryoichi
Maruyama Megumi
Nagai Mizuki
Ohno Kanji
Ebara Corporation
Talbot Brian K.
Wenderoth , Lind & Ponack, L.L.P.
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