Method for planarizing TEOS SiO.sub.2 filled shallow isolation t

Details Method for planarizing TEOS SiO.sub.2 filled shallow isolation t Method for planarizing TEOS SiO.sub.2 filled shallow isolation t

1996-11-18

1999-02-23

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438435, 148DIG50, H01L 2176

Patent

active

058743456

ABSTRACT:
According to the present invention, there is disclosed a method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches according to a planarization main step which is comprised of three processing steps. The starting structure (10) consists of a silicon substrate (11) coated by a patterned Si.sub.3 N.sub.4 layer (12) which delineates shallow trenches (20A, 20B) with a conformal layer (22) of TEOS SiO.sub.2 formed thereon. A planarizing medium, typically two superimposed photoresist layers (24.25) is formed onto the resulting structure to provide a substantially planar surface. At this stage of the fabrication, the structure is standard. Now, this planar surface is translated by a non selective two-steps plasma etching in the TEOS SiO.sub.2 layer (22). Next, should some photoresist material remain onto the structure it would be removed. Finally, a highly selective TEOS SiO.sub.2 /Si.sub.3 N.sub.4 RIE etching step is performed which stops on the Si.sub.3 N.sub.4 layer. The preferred chemistry is C.sub.4 F.sub.8 /Ar or C.sub.4 F.sub.8 /CO/Ar mixture. There is no longer the notion of process window because both the "silicon polish" and "Si.sub.3 N.sub.4 pad residuals" type of defects are eliminated. The present method offers significant advantages in terms of final test yield improvement, cost reduction and reproducibility.

REFERENCES:
patent: 4836885 (1989-06-01), Breiten et al.
"Selective Oxide: Nitride Cry Etching in a High Density Plasma Reactor", Extended Abstracts, vol. 93/1, 1993 Princeton, New Jersey US, pp. 369-370, XP000430479.
"New Etch Process for Luna ES1 Shallow Trench Isolation (IT ETCH)", IBM Technical Disclosure Bulletin, vol. 37, No. 12, Dec. 1994 New York US, pp. 475-476, XP000568024.

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