Fishing – trapping – and vermin destroying
Patent
1991-06-03
1992-01-28
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437228, 437 89, 437 99, 437 62, H01L 21302
Patent
active
050844075
ABSTRACT:
A method is described for planarizing isolated regions (12) and active regions (22) of a semiconductor wafer (10). Semiconductor wafer (10) is provided with islands of dielectric (12) that cover portions of the semiconductor wafer (10), while leaving other portions of the semiconductor wafer (10) exposed. The dielectric islands (12) have a polysilicon layer (13) that covers the dielectric islands' (12) top surface. A blanket layer of silicon is deposited on the polysilicon layer (13) that covers the top surface of the dielectric islands and is deposited between the dielectric islands (12). Planarizing the blanket layer of epitaxial silicon is achieved by a chemical-mechanical means, thereby producing a planar surface of isolated areas (12) and active areas (22).
REFERENCES:
patent: 4462847 (1984-07-01), Thompson et al.
patent: 4566914 (1986-04-01), Hall
Boland Bernard W.
Jen-Ho Wang James
Vasquez Barbara
Barbee Joe E.
Dang Trung
Hearn Brian E.
Motorola Inc.
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