Method for planarizing high step-height integrated circuit struc

Details Method for planarizing high step-height integrated circuit struc Method for planarizing high step-height integrated circuit struc

1996-03-15

1997-10-07

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 47, 437 52, 437228, 437236, H01L 2170

Patent

active

056747730

ABSTRACT:
A method for planarizing a high step-height integrated circuit structure within an integrated circuit. There is first formed upon a semiconductor substrate a high step-height integrated circuit structure. Formed then adjoining the high step-height integrated circuit structure is a patterned Global Planarization Dielectric (GPD) layer. There is then formed upon the exposed surfaces of the semiconductor substrate, the high step-height integrated circuit structure and the patterned Global Planarization Dielectric (GPD) layer a reflowable dielectric layer. Finally, the reflowable dielectric layer is reflowed.

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patent: 5488007 (1996-01-01), Kim et al.
S. Wolf, "Silicon Processing for the VLSI Era vol 2", Lattice Press, Sunset Beach, CA, 1990, pp. 226-228.

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