Method for planarizing an insulator on a semiconductor substrate

Details Method for planarizing an insulator on a semiconductor substrate Method for planarizing an insulator on a semiconductor substrate

1994-09-30

1995-05-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 70, 437228, 216 38, 216 48, 216 62, 216 67, 216 87, 216 99, H01L 2176

Patent

active

054139538

ABSTRACT:
An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial implant layer, such as CVD oxide, oxynitride or an anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The substrate surface is then implanted with As.sup.75 or p.sup.31 ions penetrating the sacrificial implant layer and forming a implant damaged layer on the field oxide. The implant damaged layer which etches faster in a wet etch in removed selectively thereby making a more planar field oxide structure. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages. The invention also describes a method for forming more gradually sloping steps on the field oxide structure without using a sacrificial layer and a method for planarizing a CVD over a patterned conducting layer using photoresist or spin-on-glass as the sacrificial implant layer.

REFERENCES:
patent: 4514251 (1985-04-01), Van Ommen et al.
patent: 4539744 (1985-09-01), Burton
patent: 4634494 (1987-01-01), Taji et al.
patent: 4652234 (1987-03-01), Jain et al.
patent: 4962064 (1990-10-01), Haskell et al.
patent: 4965221 (1990-10-01), Dennison et al.
patent: 4988405 (1991-01-01), Martin, Jr. et al.
patent: 5019526 (1991-05-01), Yamane et al.
patent: 5169801 (1992-12-01), Saito
patent: 5204288 (1993-04-01), Marks et al.
patent: 5219766 (1993-06-01), Fukunaga
patent: 5236861 (1993-08-01), Otsu
patent: 5300463 (1994-04-01), Cathey et al.

Affiliated with

Also associated with

Rating

Method for planarizing an insulator on a semiconductor substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for planarizing an insulator on a semiconductor substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for planarizing an insulator on a semiconductor substrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1705080