Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-11-02
2002-06-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S692000, C438S697000
Reexamination Certificate
active
06410403
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the planarization of isolation layers and more particularly to the chemical-mechanical polishing (CMP) of oxide layer filling Shallow trench isolation trenches.
2) Description of the Prior Art
The advent of ULSI circuits has allowed if semiconductor manufactures worldwide to fabricated semiconductor devices to extremely compact dimensions. The formation of semiconductor devices involves the process of fabrication which provides isolation within the semiconductor device. In order to fabricated integrated circuits, devices isolated from one and another must first be formed in the silicon substrate. In fabrication of USLI, a small amount of leakage in a device can induce significant power dissipation for the overall circuit.
Trench isolation is used primarily for isolating devices in VLSI and ULSI and hence they can be considered as replacement for conventional LOCOS isolation. Shallow trench isolation has gained popularity for in compact semiconductor dimensions, such as quarter-micron technology and below. In a basic shallow trench isolation (STI) technology, shallow trenches are anisotropically etched into the silicon substrate. An oxide is deposited onto the substrate and is then planarized by chemical-mechanical polishing (CMP). Another approach is called a buried oxide with etch stop processes (BOXES). The process uses a silicon nitride etch-stop layer and a pad layer formed on the TV substrate before the oxide is deposited.
Problems associated with the formation of the STI include dishing effect of wide trenches, erosion of small nitride areas, and oxide remaining on the large nitride areas.
Shallow trench isolation (STI) chemical-mechanical polish (CMP) is important especially in DRAM, due the Array VT is very sensitive to STI leveling. The STI oxide level uniformity is influenced by chemical-mechanical polish (CMP).
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,015,757 (Tsai et al.) that discloses a three layer shallow trench isolation (STI) chemical-mechanical polish (CMP) structure (including polysilicon) and CMP method. However, this method can be further improved upon.
U.S. Pat. No. 6,090,714 (Jang et al.) shows a two layer STI CMP structure and CMP method.
U.S. Pat. No. 6,084,276 (Gambino et al.) shows a two layer STI CMP structure and CMP method.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for planarizing an isolation layer formed in a trench.
It is an object of the present invention to provide a method for planarizing an isolation layer formed in a trench using a two step CMP and a pad oxide layer, the first nitride layer, the sacrificial oxide layer and the second nitride layer CMP stop structure.
It is an object of the present invention to provide a method for planarizing an high density plasma chemical vapor deposition (HDPCVD) oxide isolation layer formed in a trench using a two step CMP and a CMP stop structure comprised of a pad oxide layer, a first nitride layer, a sacrificial oxide layer and a second nitride layer.
The invention provides a method of planarizing an isolation region. Important elements of the invention are two CMP steps and the CMP stop structure comprised of a sacrificial oxide layer and a second nitride layer. The method begins when a pad layer, a first nitride layer, a sacrificial oxide layer and a second nitride layer are formed over a substrate. A trench is formed through the pad layer, the first nitride layer, the sacrificial oxide layer, the second nitride layer and in the substrate. An isolation oxide layer is deposited filling the trench and over the second nitride layer. The oxide layer is preferably formed by a high density plasma chemical vapor deposition (HDPCVD) deposition. In a first CMP step, the oxide layer and the second nitride layer are chemical-mechanical polished down to a desired level. The second nitride layer and the sacrificial oxide layer are then removed. In a second CMP step, we chemical-mechanical polish the oxide layer and the first nitride layer so that the oxide layer is about level with the first nitride layer. Lastly, the first nitride layer and the pad layer are removed and devices are formed in the active areas.
Key elements of the invention are the two CMP steps and the CMP stop structure comprised of a sacrificial oxide layer and a second nitride layer. The second nitride layer and the sacrificial oxide layer allow the STI oxide layer to be substantially planarized by the first CMP step. Then, after the remaining second nitride layer and the sacrificial oxide layer are removed, the second CMP step planarizes the oxide to the final thickness. The thickness of pad layer and the first nitride layer determine the end thickness of the STI oxide (isolation oxide) above the substrate surface. The invention's two CMP steps substantially reduce dishing of the STI oxide in wide STI areas. The invention is especially suited to planarize STI oxide formed by HDPCVD process (simultaneous deposition and sputtering).
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 5866466 (1999-02-01), Kim et al.
patent: 6015757 (2000-01-01), Tsai et al.
patent: 6030898 (2000-02-01), Liu
patent: 6084276 (2000-07-01), Gambino et al.
patent: 6090714 (2000-07-01), Jang et al.
patent: 6143635 (2000-11-01), Boyd et al.
patent: 6187650 (2001-02-01), Wu et al.
patent: 6228771 (2001-05-01), Allers
patent: 6239040 (2001-05-01), Chen
patent: 359136943 (1983-01-01), None
patent: 361008943 (1986-01-01), None
Ackerman Stephen B.
Niebling John F.
Pompey Ron E.
ProMos Technologies Inc.
Saile George O.
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