Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2002-06-07
2004-02-10
Nguyen, George (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S060000, C438S257000
Reexamination Certificate
active
06688969
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 91107422, filed Apr. 12, 2002.
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a method for planarizing a semiconductor device. More particularly, the present invention relates to a method for planarizing the dielectric layer of a flash memory device.
2. Description of Related Art
Chemical-mechanical polishing (CMP) is one of the techniques used to provide a global planarization in the manufacturing of Ultra Large Scale Integrated-Circuits. The essence of a CMP process includes a rotating polishing platen and a wafer holder, which can both exert a force on the wafer and rotate the wafer independent of the rotation of the platen. A chemical reagent also accompanies the polishing such that the topography is removed and a good uniformity across the entire surface is maintained.
The chemical reagent used in chemical mechanical polishing is known as polishing slurry. The polishing slurry consists of colloidal silica or dispersed alumina in an alkaline potassium hydroxide (KOH) or ammonium hydroxide (NH
4
OH) solution. The basic polishing mechanism for polishing a material on a wafer includes chemically altering the material to be polished and removing the chemically altered material based on the mechanical abrasion of the slurry.
FIGS. 1A through 1F
are schematic, cross-sectional views, illustrating the successive steps in polishing the dielectric layer of a flash memory device according to the prior art.
As shown in
FIG. 1A
, polysilicon gate structures
102
are formed on a substrate
100
, wherein the polysilicon gate structures comprise a silicon nitride layer formed thereon.
Referring to
FIG. 1B
, a dielectric layer
106
, for example, a silicon nitride layer, is formed on the substrate
100
, filling the space between the gate structures
102
and covering the silicon nitride layer
104
.
Thereafter, as shown in
FIG. 1C
, an alignment key oxide dipping (AOD) process is conducted to remove a majority of the dielectric layer
106
on the gate structures
102
. An oxide dip is further conducted to remove a portion of the dielectric layer
106
to expose a corner
108
of the silicon nitride layer
104
. The dielectric layer
106
is thereby resulted in the dielectric layer
106
a
that fills the space between the polysilicon gate structures
102
and the dielectric layer
106
b
that covers the silicon nitride layer
104
. Subsequently, a silicon nitride layer
110
is deposited on the substrate
100
.
Continuing to
FIG. 1D
, chemical mechanical polishing is conducted to planarize the silicon nitride layer
110
and the dielectric layer
106
b
. An oxide dip is further used to remove the metal ions and to increase the reliability of the device, wherein the metal ions are resulted from the potassium hydroxide solution used in chemical mechanical polishing. The dielectric layer
106
b
removed by the oxide dip is about 100 angstroms thick.
As shown in
FIG. 1E
, the dielectric layer
106
b
is removed.
As shown in
FIG. 1F
, the silicon nitride layers
110
,
104
are removed.
In the aforementioned conventional technique, an AOD process is conducted before the planarization process. An oxide dip is used to remove a part of the dielectric layer
106
to expose a corner of the silicon nitride layer
104
. A silicon nitride layer
110
is then deposited on the dielectric layer
106
a
&
106
b
, followed by performing the CMP process. The conventional approach is thus complicated and time consuming.
SUMMARY OF THE INVENTION
The invention provides a method to planarize the dielectric layer of a flash memory device, wherein the number of the processing steps are reduced to simplify the overall manufacturing process. The penetration of the metal ions into the substrate is prevented, wherein the metal ions are contained in the slurry used in the convention CMP approach. As a result, a reduction of the reliability of the device is also prevented
The present invention provides a method for planarizing the dielectric layer of a flash memory device, wherein this method includes forming a plurality of gate structures on a flash memory substrate. The gate structures further comprise a protective layer formed thereon. A dielectric layer is further formed on the flash memory substrate. The dielectric layer fills the space between the gate structures and covers the protective layer. Thereafter, using the protective layer as the polishing endpoint layer, chemical mechanical polishing is then conducted using a fixed polishing pad and a slurry that does not contain metal ions to planarize the dielectric layer. The fixed polishing pad includes a base and polishing abrasives, which are fixed and evenly distributed on the base.
According to the present invention, the fixed polishing abrasive technique is applied to perform the planarization process. As a result, many processing steps in the conventional practice can be omitted to simplify the entire manufacturing process and to reduce the manufacturing cost. Furthermore, since metal ions are absent in the slurry used as the polishing agent in the present invention, the reliability of the device increases.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5441598 (1995-08-01), Yu et al.
patent: 5692950 (1997-12-01), Rutherford et al.
patent: 6039633 (2000-03-01), Chopra
patent: 6354919 (2002-03-01), Chopra
patent: 6431960 (2002-08-01), Walker et al.
patent: 6514821 (2003-02-01), Huang
J.C. Patents
Macronix International Co. Ltd.
Nguyen George
LandOfFree
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