Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
2006-08-01
2011-11-01
Talbot, Brian K (Department: 1715)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C427S097700, C427S098400, C427S430100, C257S778000, C228S180100, C228S180220
Reexamination Certificate
active
08048479
ABSTRACT:
A method for placing material onto a target board by means of a transfer board comprising a plurality of blind holes, the method comprising the steps of immersing the transfer board in a material bath, wherein a first pressure acts on the material bath and a second pressure acts in the blind holes, and wherein the first pressure and the second pressure are substantially equal; generating a pressure difference between the first pressure and the second pressure, so that the blind holes of the transfer board are filled at least partially with the liquid material; extracting the transfer board from the material bath; and positioning the transfer board opposite to the target board, the material being expelled from the blind holes, such that the material touches the target board.
REFERENCES:
patent: 5834062 (1998-11-01), Johnson et al.
patent: 5899376 (1999-05-01), Tatumi et al.
patent: 6136047 (2000-10-01), Karasawa et al.
patent: 6531025 (2003-03-01), Lender et al.
patent: 6812549 (2004-11-01), Umetsu et al.
patent: 7829380 (2010-11-01), Irsigler et al.
patent: 2002/0094604 (2002-07-01), Hayama et al.
patent: 2002/0100972 (2002-08-01), Kitajima et al.
patent: 2003/0000084 (2003-01-01), Bourrieres et al.
patent: 2005/0035453 (2005-02-01), Ho et al.
patent: 1 329 949 (2003-07-01), None
patent: 1 655 389 (2006-05-01), None
patent: 3138942 (1991-06-01), None
patent: 11-298138 (1999-10-01), None
patent: 2001-060654 (2001-03-01), None
patent: 2002-270718 (2002-09-01), None
patent: 2003-218200 (2003-07-01), None
patent: 2004-296488 (2004-10-01), None
Examination Report mailed on Feb. 27, 2007, for German Patent Application No. 10-2006-035-865.
Satoh, Akinobu (2001). “Wiring of Bumpless, Three-dimensional Integrated Si Wafers Block Using Through-hole Interconnections,” Jpn.J. Appl. Phys. 40(8):4474-4780.
Buetow, M. “IBM Updates C4 Flip Chip Concept,” located at <http://circuitassembly.com/cms/index2.php?option=com—content&task=view&id=1840&Itemid=95&p...>visited on Jul. 25, 2005. (1 page).
Gruber, P. A. et al. (2005). “Low-cost Wafer Bumping,”IBM J. Res. &Dev. 49(4/5):621-639.
Lehmann, V. (1993). “The Physics of Macropore Formation in Low Doped n-Type Silicon,”J. Electrochem. Soc., 140(10):2836-2843.
Lehmann, V. et al. (2002). “MEMS Techniques Applied to the Fabrication of Anti-scatter Grids for X-ray Imaging,”Sensors&Actuators A95:202-207.
Translation of Japanese Examination Report dated Aug. 4, 2009.
Hedler Harry
Irsigler Roland
Lehmann Volker
Lehmann, legal representative Judith
Patterson & Sheridan LLP
Qimonda AG
Talbot Brian K
LandOfFree
Method for placing material onto a target board by means of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for placing material onto a target board by means of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for placing material onto a target board by means of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4306383