Boots – shoes – and leggings
Patent
1990-12-13
1994-05-03
Cosimano, Edward R.
Boots, shoes, and leggings
364488, G06F 1520
Patent
active
053093704
ABSTRACT:
Inter-area connectors are optimally placed on peripheries of bounded areas within an integrated circuit. Once circuit components are placed upon the integrated circuit, global optimum paths for connector lines between signal connectors within all the circuit components are calculated. This may be performed by calculating a global optimum rectilinear spanning tree for each net of signal connectors. Once the global optimum paths are calculated, inter-area connectors are placed at each location on a periphery of any of the circuit components where a global optimum path crosses the periphery. Finally, connector lines may be placed along the global optimum paths. For signal connectors and inter-area connectors within each circuit component, internal connector lines are routed between signal connectors along the global optimum paths within the circuit component. Also, between the circuit components, inter-area connector lines are routed between inter-area connectors along the global optimum paths.
REFERENCES:
patent: 4615011 (1986-09-01), Linsker
patent: 4630219 (1986-12-01), DiGiacomo et al.
patent: 4777606 (1988-10-01), Fournier
patent: 4852016 (1989-07-01), McGehee
patent: 4910680 (1990-03-01), Hiwatashi
patent: 5019997 (1991-05-01), Haller
patent: 5072402 (1991-12-01), Ashtaputre et al.
patent: 5079717 (1992-01-01), Miwa
patent: 5151868 (1992-09-01), Nishiyama et al.
Sara Baase, "Computer Algorithms, Introduction to Design and Analysis", Addison-Wesley Publishing Company, Reading Massachusetts, 1978, pp. 127-136.
Charles Ng, et al. A Hierarchical Floor-Planning, Placement, and Routing Tool for Sea-of-Gates Designs, IEEE 1989 Customs Integrated Circuits Conferences, pp. 3.3.1-3.3.4.
David Hsu, et al., The ChipCompiler, An Automated Standard Cell/Macrocell Physical Design Tool, IEEE 1987 Custom Integrated Circuits Conference, pp. 488-491.
Cosimano Edward R.
VLSI Technology Inc.
Weller Douglas L.
LandOfFree
Method for placement of connectors used interconnecting circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for placement of connectors used interconnecting circuit , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for placement of connectors used interconnecting circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2120194