Method for place and route of multicore chip

Details Method for place and route of multicore chip Method for place and route of multicore chip

2011-03-29

2011-03-29

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S120000, C716S123000, C716S124000, C716S125000, C716S126000

Reexamination Certificate

active

07917878

ABSTRACT:
A number of virtual regionalization lines are laid out across a chip such that the virtual regionalization lines delineate a plurality of regions on the chip. One of the plurality of regions on the chip is designated as a master region and each of a remainder of the plurality of regions on the chip is designated as a duplicate region. A number of functional blocks are placed in the master region. Each of the functional blocks is replicated in each duplicate region by placing each functional block in each duplicate region so as to be symmetric with the corresponding functional block in the master region about the virtual regionalization lines. Wires are routed in the master region. The wires routed in the master region are replicated in each duplicate region so as to be symmetric about the virtual regionalization lines.

REFERENCES:
patent: 2006/0031803 (2006-02-01), Eichenseer et al.

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