Method for pitch reduction

Details Method for pitch reduction Method for pitch reduction

2002-01-07

2003-10-28

Alanko, Anita (Department: 1765)

Etching a substrate: processes

Masking of a substrate using material resistant to an etchant

Masking of sidewall

C216S049000, C216S051000, C216S072000, C438S696000, C438S946000, C438S947000, C438S952000

Reexamination Certificate

active

06638441

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for pitch reduction, and more particularly to a method for forming a device structure with a tiny dimension.
2. Description of the Related Art
In semiconductor manufacture, microlithography technologies are used in the formation of integrated circuits on a semiconductor wafer. During a lithographic process, a form of radiant energy, such as ultraviolet light, is passed through a mask or reticle and onto the semiconductor wafer. The reticle contains opaque and transparent regions formed in a desired pattern. A grating pattern, for instance, may be used to define parallel spaced conducting lines on a semiconductor wafer. The ultraviolet light exposes the reticle pattern on a layer of resist formed on the wafer. The resist is then developed for removing either the exposed portions of resist for a positive resist or the unexposed portions of resist for a negative resist. The patterned resist can then be used during a subsequent semiconductor fabrication process such as ion implantation or etching.
As microcircuit densities have increased, the size of the features of semiconductor devices have decreased to the submicron level. These submicron features may include the width and spacing of metal conducting lines or the size of various geometric features of semiconductor devices. The requirement of submicron features has necessitated the development of improved microlithographic processes and systems. As an example, phase shifting microphotolithographic processes use phase shifting reticles to phase shift the exposure radiation at the edges of a pattern to increase the image contrast. Other sub-micron microlithographic processes include e-beam lithography technologies and x-ray lithography technologies.
However, the native limits of the sub-micron microlithographic processes mentioned above are still unavoidable and are hard to overcome. As the size scale of various geometric features of semiconductor devices reaches 0.18 micron, 0.13 micron or even a tinier scale, the problems will be tougher and hence there is a need for new strategy to overcome the native limits of modern sub-micron microlithographic processes till the unveiling the new and revolutionary processes.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for pitch reduction that can shrink the line width of modern integrated circuits further with available photolithography technologies.
It is another object of this invention to provide a method for pitch reduction that can form a pattern with a pitch ⅓ the original pitch formed by available photolithography technologies.
It is a further object of this invention to provide a method for pitch reduction having outstanding critical dimension and line position controls and without problems of complexity and overlay.
In one embodiment of this invention, the invention uses a method for pitch reduction, the method can form a pattern with a pitch ⅓ the original pitch formed by available photolithography technologies by only using one photo mask or one pattern transfer process, self-aligned etching back processes, and conventional deposition processes. By choosing appropriate layers to be deposited and etched, the pattern can be an etching mask or it can be a device structure itself. The method comprises the steps of providing a substrate having a pattern of a photoresist layer thereon, wherein said pattern comprises a plurality of equidistance lines and the width of each said equidistance line equals to the pitch of two adjacent said equidistance lines, forming a first layer over said pattern and said substrate; etching back said first layer to expose said substrate, forming a second layer over said pattern, said first layer and said substrate, etching back said second layer to expose said pattern and said first layer, removing said pattern, forming a third layer over said first layer, said second layer and said substrate; etching back said third layer to expose said substrate, forming a fourth layer over said first layer, said second layer, said third layer and said substrate, wherein the material of said fourth layer is the same with the material of said first layer, etching back said fourth layer to expose said first layer, said second layer and said third layer, and removing said second layer and said third layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5420067 (1995-05-01), Hsu
patent: 5618383 (1997-04-01), Randall
patent: 5795830 (1998-08-01), Cronin et al.
patent: 6063688 (2000-05-01), Doyle et al.
patent: 6093627 (2000-07-01), Sung
patent: 6337266 (2002-01-01), Zahorik
patent: 6413812 (2002-07-01), Harshfield
patent: 6482731 (2002-11-01), Juengling

Affiliated with

Also associated with

Rating

Method for pitch reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for pitch reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for pitch reduction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3162025