Method for physical VLSI-chip design

Details Method for physical VLSI-chip design Method for physical VLSI-chip design

1987-12-15

1989-12-26

Lall, Parshotam S.

Boots, shoes, and leggings

364490, 364489, 364488, G06F 1560

Patent

active

048902381

ABSTRACT:
For the physical design of a very large scale integration (VSLI) chip, a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology, the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus, the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.

REFERENCES:
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4608649 (1986-08-01), Dowis et al.
patent: 4612618 (1986-09-01), Pryor et al.
patent: 4613940 (1986-09-01), Shenton et al.
patent: 4630219 (1986-12-01), DiGiacomo et al.
patent: 4713773 (1987-12-01), Cooper et al.

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