Method for performing transistor-level static timing analysis of

Details Method for performing transistor-level static timing analysis of Method for performing transistor-level static timing analysis of

1997-01-21

1999-08-31

Teska, Kevin J.

G06F 1750

Patent

active

059464755

ABSTRACT:
A method is provided for statically computing delays for transistor-level logic circuits which have input signal dependencies. This methodology may be implemented in transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors.

REFERENCES:
patent: 4827428 (1989-05-01), Dunlop et al.
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5095454 (1992-03-01), Huang
patent: 5191541 (1993-03-01), Landman et al.
patent: 5222030 (1993-06-01), Dangelo et al.
patent: 5323401 (1994-06-01), Maston
patent: 5365463 (1994-11-01), Donath et al.
patent: 5475605 (1995-12-01), Lin
patent: 5475607 (1995-12-01), Apte et al.
patent: 5493508 (1996-02-01), Dangelo et al.
patent: 5508937 (1996-04-01), Abato et al.
patent: 5787008 (1998-07-01), Pullela et al.
Norman P. Jouppi, Timing Analysis for nMOS VLSI, IEEE, 0738-100X/83/0000/0411, 1983.
Bryant, Randal E., "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Transactions on Computers, vol. C-35, vol. 8, Aug. 1986, pp. 677-691.
Dagenais, Michel R., et al., "Transistor-Level Estimation of Worst-Case Delays in MOS VLSI Circuits," IEEE Transactions on Computer-Aided Design, vol. 11, No. 3, Mar. 1992, pp. 384-395.
Desai, Madhav P., et al., "A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation," 33rd Design Automation Conference, ACM, Inc., 1996.
Hitchcock, Sr., Robert B., et al., "Timing Analysis of Computer Hardware," IBM J. Res. Develop., vol. 26, No. 1, Jan. 1982, pp. 100-105.
Jouppi, Norman P., "Timing Analysis and Performance Improvement of MOS VLSI Designs," IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 4, Jul. 1987, pp. 650-665.
Ousterhout, John K., "Crystal: A Timing Analyzer for nMOS VLSI Circuits," Proc. Third Cal-Tech VLSI Conf., Computer Sciences Press, 1983, pp. 57-69.
Pillage, Lawrence T., "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Transactions on Computer-Aided Design, vol. 9, No. 4, Apr. 1990, pp. 352-366.
Ratzlaff, Curtis L., et al., "RICE: Rapid Interconnect Circuit Evaluator," 28th ACM/IEEE Design Automation Conference, Paper 33.1, 1991, pp. 555-560.
Ratzlaff, Curtis L., et al., RICE Toolkit Reference Manual, Version 4.0, Computer Engineering Research Center, The University of Texas at Austin, Austin, Texas, Sep., 1992.

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