Method for performing timing analysis of a clock circuit

Details Method for performing timing analysis of a clock circuit Method for performing timing analysis of a clock circuit

1996-11-27

2000-01-11

Teska, Kevin J.

39550007, 39550034, G06F 1750

Patent

active

060145102

ABSTRACT:
A method for accurately and precisely computing the output signal transition times in a clock distribution, or buffering, network of a data processing system is provided herein. This methodology may be implemented in transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. Furthermore, the static timing analysis techniques traditionally implemented are modified to more accurately compute signal delays and transition times at the outputs of a clock distribution network circuit.

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