Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Patent
1996-03-04
2000-05-30
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
712208, 711210, 711211, G06F 700
Patent
active
060702370
ABSTRACT:
A novel processor for manipulating packed data. The packed data includes a first data element D1 and a second data element D2. Each of said data elements has a predetermined number of bits. The processor comprises a decoder, a register, and a circuit. The decoder is for decoding a control signal responsive to receiving the control signal. The register is coupled to the decoder. The register is for storing the packed data. The circuit is coupled to the decoder. The circuit is for generating a first result data element R1 and a second data element R2. The circuit is further for generating R1 to represent a total number bits set in D1, and the circuit is further for generating R2 to represent a total number bits set in D2.
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Eitan Benny
Mennemeier Larry
Mittal Millind
Peleg Alexander
Yaari Yaakov
An Meng-Ai T.
Intel Corporation
Nguyen Dzung C.
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