Method for performing model checking in integrated circuit desig

Details Method for performing model checking in integrated circuit desig Method for performing model checking in integrated circuit desig

1997-12-31

1999-12-07

Teska, Kevin J.

39550006, G06F 1750

Patent

active

059997176

ABSTRACT:
A method is presented for performing model checking of an integrated circuit design that avoids the need for construction of an environment model by the use of constraints (44). The method supports an assume/guarantee style of reasoning to ensure that the constraints (44) are a true abstraction of the actual environment in which the integrated circuit is designed to operate. The constraints (44) may be used to provide primary inputs for a design under analysis (DUA) (16). Also, the constraints (44) may refer to internal states and to outputs of the DUA (16). In addition, monitors (42) may be used to monitor the inputs to the DUA (16). The constraints (44) can then be used with the monitors (42) to specify complex sequential environment properties.

REFERENCES:
patent: 5696771 (1997-12-01), Beausang et al.
patent: 5751593 (1998-05-01), Pullela et al.
patent: 5790415 (1998-08-01), Pullela et al.
David E. Long, "Model Checking, Abstraction, and Compositional Verification", Thesis for the degree of Doctor of Philosophy, School of Computer Science, Pittsburgh, PA, Jul. 1993, (12pp.), Chapter 2 "Compositional Verification Part I", pp.21-58, Chapter 3 "Compositional Verification Part II", pp. 59-90.
Edmund M. Clarke et al., "Design and Synthesis of Synchronization Skeletons Using Branching Time Temporal Logic", Aiken Computation Laboratory, Harvard University, Cambridge, Mass., 20 pp.

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