Method for performing integrated section-level and full-chip tim

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364578, G06F 1750

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active

055463207

ABSTRACT:
A method for performing integrated section-level and full-chip timing verification is employed for integrated circuit designs that include several section designs. A plurality of bristle timing parameters define timing relationships between the section designs. A section-level verification procedure is performed for each of the section designs to determine whether the section designs conform to predetermined intra-section timing constraints. A full-chip verification procedure is performed for the integrated circuit design to determine the bristle timing parameters and to determine whether the integrated circuit design conforms with predetermined intersection timing constraints.

REFERENCES:
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patent: 4924430 (1990-05-01), Zasio et al.
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5237514 (1993-08-01), Curtin
"Analytical Power/Timing Optimization Technique for Digital System" by Puehli et al., IEEE 14U Design Automation Conf., 1977, pp. 142-146.
"Timing Analysis for nMOS VLSI" by N. P. Jouppi, IEEE 20th Design Automation Conf., 1983, pp. 411-418.

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