Method for performing functional comparison of combinational cir

Details Method for performing functional comparison of combinational cir Method for performing functional comparison of combinational cir

1997-08-28

2000-03-07

Teska, Kevin J.

39550019, G06F 1750

Patent

active

060351071

ABSTRACT:
A verification technique which is specifically adapted for formally comparing large combinational circuits with some structural similarities. The approach combines the application of Binary Decision Diagrams (BDDs) with circuit graph hashing, automatic insertion of multiple cut frontiers, and a controlled elimination of false negative verification results caused by the cuts. Multiple BDDs are computed for the internal nets of the circuit, originating from the cut frontiers, and the BDD propagation is prioritized by size and discontinued once a given limit is exceeded. The resulting verification engine is reliably accurate and efficient for a wide variety of practical hardware designs ranging from identical circuits to designs with very few similarities.

REFERENCES:
patent: 5649165 (1997-07-01), Jain et al.
patent: 5754454 (1998-05-01), Pixley et al.
Mukherjec et al.: "Efficient Combinational Verification Using BDDs and a Hash Table"; 1997 IEEE Int. Symp. Circuits and Systems, pp. 1025-1028, Jun. 1997.

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