Method for performing efficient memory testing on large memory a

Details Method for performing efficient memory testing on large memory a Method for performing efficient memory testing on large memory a

1995-06-07

1997-01-07

Nguyen, Hoa T.

395445, G06F 1100

Patent

active

055926169

ABSTRACT:
In connection with a computer system, a method for performing efficient memory testing of large memory arrays in a single contiguous block is disclosed. Memory test code normally residing in ROM or flash memory is copied to a processor's primary (L1) cache via the processor's test registers. Once contained in the processor's L1 cache, the memory test code is executed to test all of system memory in a single, contiguous block, allowing a more complete test for memory-related faults. The method results in greatly improved performance because the only accesses external to the processor are memory test accesses, and because cache memory is typically high-speed as compared to RAM, ROM or flash memory.

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