Method for patterning and etching a passivation layer

Details Method for patterning and etching a passivation layer Method for patterning and etching a passivation layer

2005-09-20

2009-02-24

Dang, Phuc T (Department: 2892)

Semiconductor device manufacturing: process

Chemical etching

C438S612000, C438S687000

Reexamination Certificate

active

07494928

ABSTRACT:
A method for patterning passivation layers including providing a semiconductor wafer comprising metal interconnects; forming a dielectric passivation layer on the metal interconnects; forming a photosensitive polymeric passivation layer on the dielectric passivation layer; patterning the photosensitive polymeric passivation layer in a first patterning process to form a first opening revealing a portion of the dielectric passivation layer; and, patterning the portion of the dielectric passivation layer in a second patterning process to form at least a second opening in the dielectric passivation layer.

REFERENCES:
patent: 5229257 (1993-07-01), Cronin et al.
patent: 6635585 (2003-10-01), Khe et al.
patent: 6660624 (2003-12-01), Tzeng et al.

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