Method for patterning a metallization layer by reducing...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S624000, C438S625000, C438S637000, C438S694000, C438S734000, C257SE21257, C257SE21579

Reexamination Certificate

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08048811

ABSTRACT:
By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree of etch selectivity during the patterning of openings in a metallization layer of a semiconductor device.

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Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 016 425.9 dated Jul. 14, 2009.

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