Method for parallel testing of semiconductor devices

Details Method for parallel testing of semiconductor devices Method for parallel testing of semiconductor devices

1989-11-03

1991-04-30

Wieder, Kenneth

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 725, 324158F, G01R 102, G01R 1067

Patent

active

050121871

ABSTRACT:
A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines formed on the membrane test head. The semiconductor memory has a plurality of contact pads thereon which are coupled to the probes. In this manner, a plurality of semiconductor memories can be tested in wafer form. Alternatively, individual semiconductor memory chips can be mounted on a receiver plate and tested individually or in parallel by moving the receiver plate so that the contact pads couple to the probes.

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"Membrane Probe Card Technology", by Leslie et al., IEEE Internat. Test Conf., 12/1988, Paper 30.1, pp. 601-607.

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