Method for packaging a semiconductor chip

Details Method for packaging a semiconductor chip Method for packaging a semiconductor chip

2000-05-05

2001-06-05

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S126000, C438S127000

Reexamination Certificate

active

06242284

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for packaging a semiconductor chip; more particularly, the present invention relates to a method for packaging a semiconductor that generally forms larger upper portions of the leads relative to lower portions of the leads.
2. Description of the Prior Art
Microelectronic devices are typically comprised of one or more silicon die having, at least in part of, a multitude of die bond pads on a front surface, a chip body, and an interconnection scheme to connect the pads on the die to a supporting substrate and an encapsulating to ensure that the die is protected from contaminants. The combination of these elements is generally referred to as a chip package.
However, the pin count of a package such as DIP (dual inline package) according to a conventional packaging method typically is not high enough. Thus, the latest trend has been emphasized on a BGA (ball grid array) package as shown in
FIG. 1
, which is developed to address the need for a package of increased pin count such that the dimensions of the package are nearly identical to those of the chip being packaged therein.
Referring to
FIG.1
, in which a packaged semiconductor chip structure
10
of a prior art is disclosed by the Taiwanes Patent No. 348306 as a preferred embodiment. The packaged semiconductor chip structure
10
includes a chip
11
encapsulated by a molding material
12
. Furthermore, a plurality of bonding pads
11
a
, which are electrically connected to a plurality of leads
13
, are formed on the top surface of the chip
11
. A conducting adhesive layer
14
, which is exposed from the lower portion of the molding material
12
, is adhered to the bottom surface of the chip
11
via the top. The leads
13
are exposed on the bottom surface of the molding material
12
and outside the periphery of the chip
11
for electrical connection to external circuits (not shown). Nonetheless, since the exposed leads
13
are not completely encapsulated by the molding material
12
, the leads
13
can not be anchored securely by the encapsulation.
Furthermore, since only the top side of the chip
11
is completely sealed by the encapsulation of the molding material
12
and the bottom side thereof exposed, moisture and/or ionic contaminants from the immediate environment may damage the packaged semiconductor chip
10
. As a result, the reliablity of the packaged semiconductor chip
10
is diminished as well as the expected life cycle of the chip
11
. As the trend for the semiconductor industry is towards packaging IC devices of increasingly smaller size, it is therefore important that an IC package design capable of solving the above problems is devised.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide a packaging method that can solve the abovementioned problems.
To achieve the object of the invention, a method for packaging a semiconductor chip on a conducting substrate is provided. The method according to the present invention comprises the following steps of: (a) forming a plurality of openings on the top surface of the conducting substrate, wherein the upper portions of the openings are formed larger than the lower portions of the openings; (b) forming insulating sections in the conducting substrate by filling an insulating material in the openings; (c) forming a plurality of leads insulated by the insulating sections by planarizing the bottom surface of the conducting substrate to expose and form planarized bottom surfaces of the insulating sections; (d) mounting a semiconductor chip on the bottom surface of the conducting substrate; (e) providing a plurality of conducting wires to electrically connect the semiconductor chip to the leads; and (f) encapsulating the semiconductor chip and the conducting wires.
Another method for packaging a semiconductor chip on a conducting substrate that includes a chip region and a lead region, whereas the method comprises the following steps of:(a) forming a plurality of openings on the top surface of the lead region, wherein the upper portions of the openings are larger than the lower portions of the openings; (b) forming insulating sections in the conducting substrate by filling an insulating material in the openings; (c) forming a plurality of leads insulated by the insulating sections in the lead region by planarizing the bottom surface of the conducting substrate to expose and form planarized bottom surfaces of the insulating sections; (d) mounting a semiconductor chip on the chip region of the bottom surface of the conducting substrate; (e) providing a plurality of conducting wires to electrically connect the semiconductor chip to the leads; and (f) encapsulating the semiconductor chip and the conducting wires.
Furthermore, the conducting substrate is turned upside down so that the upper portions of the leads are larger than the lower portions of the leads, which makes the leads less likely to be detached from the substrate and the destruction caused by water less likely to occur, thus the reliability of the package can be increased.


REFERENCES:
patent: 5930603 (1999-07-01), Tsuji et al.
patent: 5989935 (1999-11-01), Abbott
patent: 6020218 (2000-02-01), Shim et al.

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