Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-08-13
2004-12-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S113000, C438S114000, C438S127000
Reexamination Certificate
active
06830956
ABSTRACT:
This application claims priority from Japanese patent application number 13(2001)-245359, filed Aug. 13, 2001.
FIELD OF THE INVENTION
The present invention pertains to a semiconductor device manufacturing method. More specifically, it pertains to a semiconductor device manufacturing method that lowers the profile of semiconductor devices, and that improves the productivity and the measurement accuracy of the semiconductor devices during the production of semiconductor devices in which the semiconductor chips are mounted face down (flip chip) onto a substrate.
BACKGROUND OF THE INVENTION
As portable telephone units, portable computers, and other compact electronic equipment become more popular, there is a growing need for compact low-profile semiconductor devices to be installed in them. As a chip mounting method for producing compact semiconductor devices, a flip-chip method in which semiconductor chips are mounted face down onto a substrate is available. With said method, the semiconductor devices can be made more compact than with a wire bonding method in which semiconductor chips mounted face up onto the substrate are connected to the substrate by means of wire bonding because areas for achieving electrical connection between the semiconductor chips and the substrate can be housed within the chip size.
With the flip-chip method, the semiconductor devices are produced by the following steps; that is, multiple semiconductor chips are mounted onto a substrate having adjoining multiple chip mounting areas with their functional planes facing the plane of said substrate, a molding resin is injected onto the aforementioned substrate in order to form a resin sealed block in which the aforementioned multiple semiconductor chips are sealed, bump electrodes for mounting the aforementioned semiconductor devices onto an external substrate are formed on the bottom of the aforementioned substrate, and the aforementioned resin sealed block is diced into individual semiconductor devices. They have a layered structure of the kind shown in
FIG. 5
in terms of their profile.
To make aforementioned semiconductor device P low-profile, respective layers A-E constituting semiconductor device P need to be made as thin as possible. However, while studies are being conducted to make chip mounting bump layer C, substrate layer D, and external substrate mounting bump layer E thinner, their threshold values are about to be reached, and no more drastic low-profiling can be expected. In addition, molding resin layer A (coating layer on the non-functional plane of the chip) is formed in a space between the non-functional planes of the semiconductor chips and the mold. Thus, if said space is eliminated, the flow of the molding resin in the mold gets hindered, resulting in a risk of a productivity decrease and molding deficiency. In addition, the thickness of semiconductor chip layer B is determined in consideration of the steps (for example, plated bumps) prior to their mounting onto the substrate and the handling of the semiconductor chips during the substrate mounting step. Thus, if it is made too thin, cracks occur during the handling and result in a decrease in the yield.
Accordingly, a suggestion may be made that the top side (non-functional plane side) of aforementioned semiconductor device P is ground to make it thin while it is in the resin sealed block stage. However, because the resin sealed block has the aforementioned layered structure, it is likely to get warped due to the shrinkage of the molding resin and the difference in the thermal expansion coefficients of the respective layers. Thus, the resin sealed block cannot be secured firmly, and the amount of the grinding becomes uneven, so that the thickness accuracy of the semiconductor device may be deteriorated. Moreover, 2 tape application steps are needed a retaining tape needs to be put on the plane used to fix the resin sealed block during the grinding of the resin sealed block; and the retaining tape needs to be applied during the dicing step. As a result, not only the production process gets complicated, but there is also a problem that the amount of the tape used increases.
Therefore, the purpose of the present invention is to present a semiconductor device manufacturing method by which not only the semiconductor device can be low-profiled by grinding the resin sealed block, but uniform grinding can also be realized by eliminating the warpage of the resin sealed block, and simplification of the production process and reduction in the amount of the tape used can be realized by reducing the tape application step.
SUMMARY OF THE INVENTION
In order to achieve the aforementioned goal, the semiconductor device manufacturing method pertaining to the present invention involves a step in which multiple semiconductor chips are mounted onto on a substrate having adjoining multiple chip mounting areas with their functional planes facing the mounting plane of the aforementioned substrate, a step in which a molding resin is injected onto the aforementioned substrate in order to form a resin sealed block in which the aforementioned multiple semiconductor chips are sealed, a step in which the aforementioned resin sealed block is cut halfway to a prescribed depth from the side of the aforementioned substrate along lines separating the aforementioned chip mounting areas from each other in order to form cut recesses, and a step in which the aforementioned resin sealed block is ground from the side of the aforementioned molding resin at least until the aforementioned cut recesses are reached in order to separate it into individual semiconductor devices.
In addition, it is preferable that a step in which electrodes are formed on the plane opposite to the semiconductor mounting plane of the aforementioned substrate to serve as external connection terminals for the aforementioned semiconductor devices is provided before the aforementioned halfway cutting step. In such case, handling of the resin sealed block during the formation of the bump electrodes can be made easier by forming the external substrate mounting bump electrodes (external connection terminals) before the resin sealed block is cut halfway.
In addition, it is preferable that the depth of the aforementioned cut recesses is 30% or less of that of the aforementioned molding resin in the aforementioned halfway cutting step. In such case, bending of the resin sealed block can be prevented by securing a minimum connecting strength.
In addition, it is preferable that the aforementioned halfway cutting step includes a step in which the aforementioned molding resin is fixed by suction using a suction device when forming the aforementioned cut recesses. The aforementioned grinding step includes a step in which a retaining tape is put on the aforementioned substrate when separating the aforementioned semiconductor devices and a step in which the aforementioned resin sealed block is fixed by suction via the aforementioned retaining tape using a suction device. In such case, the retaining tape application step is required only once, so that not only the production process can be simplified, but the amount of the retaining tape used can also be reduced.
In addition, it is preferable that the aforementioned molding resin and the aforementioned semiconductor chips are ground during the aforementioned grinding step in such a manner that the thickness of the aforementioned semiconductor chips after the grinding becomes 60% or less of that before the grinding. In such case, there is no need to form thin semiconductor chips thin prior to the mounting of the semiconductor chips onto the substrate, the problem of cracks in the semiconductor chips during the handling of the semiconductor chips before they are mounted onto the substrate can be avoided, and the productivity and the yield can be improved. Furthermore, the semiconductor devices can be made drastically low-profile.
In addition, it is preferable that a step in which a heat sink is provided on the ground planes of the aforementioned molding resin and the a
Masumoto Kenji
Masumoto Mutsumi
Brady W. James
Roman Angel
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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