Method for over-etching to improve voltage distribution

Details Method for over-etching to improve voltage distribution Method for over-etching to improve voltage distribution

1996-06-27

1998-07-28

Tsai, Jey

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

438600, 148DIG55, H01L 2900

Patent

active

057862400

ABSTRACT:
An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.

REFERENCES:
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 5171715 (1992-12-01), Husher et al.
patent: 5272666 (1993-12-01), Tsang et al.
patent: 5314840 (1994-05-01), Schepis et al.
patent: 5319238 (1994-06-01), Gorden et al.
patent: 5475253 (1995-12-01), Look et al.
S. Chiang, R. Foroubi, W. Chen, F. Hawley, J. McCollum, E. Hamdy, C. Hu, "Antifuse Structure Comparison for Filed Programmable Gate Arrays," International Electron Devices Meeting, pp. 24.6.1-24.6.4, Dec. 13-16, 1992.

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