Method for optimizing utilization of a cache memory

Details Method for optimizing utilization of a cache memory Method for optimizing utilization of a cache memory

1988-11-30

1991-02-05

Fleming, Michael R.

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364900, 3649571, 36496422, 3649642, 364964, 3642624, 3642543, 3642434, 36424341, 36424342, G06F 930, G06F 1300, G06F 1200

Patent

active

049910884

ABSTRACT:
A method is provided for minimizing cache misses in a compiled computer program having loop instructions. The compiled computer program is examined to identify a set of compiled loop instructions which is smaller than a cache memory block. The set of compiled loop instructions may straddle two blocks of main memory, which would cause cache misses when the program is executed. The identified set of compiled loop instructions is therefore positioned to fall entirely within the boundaries of a block of main memory so that cache misses are avoided when the set of compiled loop instructions is executed. Loop-invariant instructions are removed from the set of compiled loop instructions. When blocks of the main memory unit are mapped into the cache memory in a set-associative manner, external-call locations are mapped into different rows of the main memory then the corresponding loop instructions. As a result, when blocks of main memory are transferred to the cache memory unit, cache misses are avoided.

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patent: 4764861 (1988-08-01), Toshiterushibuya
patent: 4858115 (1989-08-01), Rusterholz et al.
patent: 4873630 (1989-10-01), Rusterholz et al.

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