Data processing: artificial intelligence – Neural network
Reexamination Certificate
1998-06-25
2002-01-08
Powell, Mark R. (Department: 2122)
Data processing: artificial intelligence
Neural network
C706S015000, C706S016000, C706S023000, C706S031000, C706S042000
Reexamination Certificate
active
06338052
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a method for optimizing matching network of semiconductor process apparatus by tuning source impedance with load impedance. More particularly, the present invention relates to a method for optimizing matching network of semiconductor process apparatus using neural network.
In many applications of semiconductor process apparatus, power source is connected to electric load. This is to maximize electric power transmitted to load. Such an object can be accomplished when output impedance of power source and input impedance of electric load have a relation of couple complex number to each other theoretically. However, in practical applications where user operates a semiconductor process apparatus, for example, a plasma etcher using radio frequency(“RF”) or microwave(“MW”) as power source and process chamber as electric load, probability that output impedance of power source have a relation of couple complex number to each other is poor. Therefore, so as to transmit maximum power to the process chamber, impedance matching network has to be established between the plasma source and the process chamber. Basically, impedance matching network acts as providing to source an impedance corresponding to couple complex number of output impedance and also acts as providing to electric load an impedance corresponding to couple complex number of input impedance. Thus, in impedance matching network are established a variable inductor and a variable capacitor electrically connected to each other. Therefore, in a case a semiconductor process apparatus is in need of impedance matching, it is controlled by complementarily handling the variable inductor and the variable capacitor.
As a merely example, two variable capacitors are established in the matching network of RF plasma source to tune the source with the load. In addition, in case of MW plasma source, three stubs are established in the tuner of the matching network, and is handled to tune impedance with electric load.
In use of such kinds of plasma sources, initial values of the matching network are fixed. For example, in case that RF plasma source is used, initial value of the two variable capacitors are fixed to a first given value, and in case MW plasma source is used, initial values of the three stubs are also fixed to a second given value.
Initial value, however, greatly affects impedance matching between source and load. This is due to difference in initial process recipes according to source electric power, gas pressure, flow rates of reactant gases, or RF power. Accordingly, it is desirable to provide an optimal method for ideal impedance matching.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to attain ideal impedance matching by automatically designating initial values of recipe for the fabrication of a semiconductor device using neural network.
According to the invention, there is provided a method for optimizing matching network between an output impedance and an input impedance in a semiconductor process apparatus. The method comprises the steps of: providing a neural network capable of being trained through repeated learning; training the neural network from previously performed process conditions; setting up an initial value; comparing the initial value with a theoretically calculated value, to obtain error between the values; and repeating the training, setting, and comparing steps until the error becomes zero.
REFERENCES:
patent: 5443688 (1995-08-01), Toure et al.
patent: 5453154 (1995-09-01), Thomas
patent: 5856722 (1999-01-01), Haronian et al.
patent: 5910011 (1999-06-01), Cruse
patent: 6045877 (2000-04-01), Gleason et al.
patent: 0047354 (1982-03-01), None
patent: 0155562 (1985-09-01), None
patent: 0685936 (1995-12-01), None
patent: 2126098 (1984-03-01), None
patent: 9724748 (1997-07-01), None
patent: 9744812 (1997-11-01), None
Card, J.P.; Sniderman, D.L.; Klimasauskas, C., Dynamic neural control for a plasma etch process, Neural Networks, IEEE Transactions on, vol. 8 4, Jul. 1997, pp. 883-.*
Rietman, E.A., A neural network model of a contact plasma etch process for VLSI production, Semiconductor Manufacturing, IEEE Transactions on, vol. 9 1, Feb. 1996, pp. 95-100.*
Kim, B.; May, G.S., Modeling reactive ion etching of silicon dioxide films using neural networks, Electronic Components and Technology Conference, 1994. Proceedings., 44th, Jan. 1994, pp. 273-278.*
Kim, B.; May, G.S., Reactive ion etch modeling using neural networks and simulated annealing, Components, Packaging, and Manufacturing Technology, Part C, IEEE Transactions on see also Components, Hybrids, and Manufacturing Technology, IEEE Transactions, Jan. 1996.*
Rietman, E.A.; Patel, S.; Lory, E., Neural network control of a plasma gate etch: Early steps in wafer-to-wafer process control, Electronic Manufacturing Technology Symposium, 1993, Fifteenth IEEE/CHMT International , Jan. 1993 , pp. 454-457.*
Erten, G.; Gharbi, A.; Salam, F.; Grotjohn, T.; Asmussen, J. Using neural networks to control the process of plasma etching and deposition, Neural Networks, 1996., IEEE International Conference on, vol. 2, Jan. 1996, pp. 1091-1096 vol. 2.*
Taek-Beom Koh; Sang-Yeob Cha; Kwang Bang Woo; Dae-Sik Moon; Development of integrated process control system utilizing neural network for plasma etching, Kyu Hwan Kwak; Ho Seung Chang Electronics Manufacturing Technology Symposium, 1995. Manufacturing Te, Jul. 1997.
Hyundai Electronics Industries Co,. Ltd.
Powell Mark R.
Selitto & Associates, P.C.
Starks Wilbert L.
LandOfFree
Method for optimizing matching network of semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for optimizing matching network of semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for optimizing matching network of semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2842780