Method for optimizing frequency of clock signal and network...

Details Method for optimizing frequency of clock signal and network... Method for optimizing frequency of clock signal and network...

2004-03-12

2008-08-12

Pham, Chi H. (Department: 2616)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S236000

Reexamination Certificate

active

07411906

ABSTRACT:
A method for optimizing frequency of a clock signal is provided for operations of a network switch. The network switch includes a clock signal generator for generating the clock signal, and a plurality of input/output ports for communicating therevia with at least one network node. Firstly, a control signal is asserted to the clock signal generator according to a certain condition of the input/output ports, e.g. the count of the I/O ports in use or the overall data transmission rate of the I/O ports in use. Then, the frequency of the clock signal outputted from the clock signal generator is adjusted in response to the control signal.

REFERENCES:
patent: 6256320 (2001-07-01), Tang et al.
patent: 6298067 (2001-10-01), Tang
patent: 6317804 (2001-11-01), Levy et al.
patent: 6442137 (2002-08-01), Yu et al.
patent: 2004/0090995 (2004-05-01), Kang et al.
patent: 1294327 (2001-05-01), None

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