Method for optimizing element sizes in a semiconductor device

Details Method for optimizing element sizes in a semiconductor device Method for optimizing element sizes in a semiconductor device

1997-03-03

1999-05-11

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, 364490, 364491, 364578, G06F19/00

Patent

active

059034718

ABSTRACT:
A slack time, based on a required and actual delay time, is calculated for each node in a circuit (302). For each element in the circuit, a sensitivity (304) and a figure of merit (306) is calculated. A variance is determined for the calculated figure of merits (308). The circuit element having the smallest absolute figure or merit is optimized when the variance is smaller than a predefined threshold (310, 312).

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US Patent Application, Satyamurthy et al., "Simulation corrected sensitivity"Serial No. 08/429,488, filed Apr. 10, 1996.
US Patent Application, Blaauw, et al., "Element Sizing for Integrated Circuits," Serial No. 08/495,061, filed Jun. 26, 1995.
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US Patent Application, Dharchoudhury, et al., "Fast Semi-Analytical Timing Simulation of MOS Circuits," Serial No. 08/629,489, filed on Apr. 10, 1996 .

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