Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
2001-11-27
2004-08-24
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C702S182000, C702S189000, C702S191000
Reexamination Certificate
active
06782347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for optimizing electromagnetic interference (EMI) and a method for analyzing the electromagnetic, and more particularly to a method for optimizing the EMI by simulation at a high speed and with great accuracy for a large scale and high speed driving LSI (large scale semiconductor integrated circuit).
2. Description of the Related Art
The LSI has been widely used in not only a computer but also a communication device such as a portable telephone, a household appliance, a toy, a motorcar, etc. However, the EMI emitted form these devices has become problematic as (EMI) for a receiver such as a television/radio and a cause for malfunction of other systems. In order to overcome these inconveniences, a measure such as filtering or shielding has been made for the entire device. However, from the standpoint of the increase in the number of components, increase in cost, difficulty in the measure for a product, etc., noise suppression in an LSI package itself has been eagerly demanded.
Under such a circumstance, in each of the products, the LSI is placed as a key device. In order to assure the ability to compete, the large-scaling and speed-up of the LSI have been demanded. As the product cycle becomes short, in order to satisfy these demands, the automation of LSI designing is indispensable. Hence, necessity of adopting synchronous designing has risen as a condition for introducing the present designing automation technology. However, the entire circuitry operates synchronously with a reference clock, and in the case of the LSI designed in a large scale and driven at a high speed, the instantaneous current becomes very large, thereby leading to an increase in the EMI.
This invention relates to a simulation technique which can maintain the large-scaling and speed-up of the LSI and permits EMI evaluation indispensable to reduce the EMI.
The noise given by the LSI is roughly classified into radiation noise and conduction noise. The noise radiated directly from the LSI includes the noise radiated from the internal wiring of the LSI. However, the internal wiring is not so large as an antenna. As the operating frequency of the LSI is improved, the noise radiated directly from the LSI may be problematic in the future. However, at present, the radiation noise within the LSI is not problematic.
On the other hand, the conduction noise influences the other devices on a printed board through direct connection such as wires within the LSI, a lead frame, package or wiring on the printed board, and noise is radiated from a source or antenna of these connecting passages. The antenna of the connecting passage is much larger than the internal wiring of the LSI so that it constitutes a dominant element from the standpoint of the EMI.
The passage of the conduction noise from the LSI includes a power source and a signal. However, in the nearby electromagnetic field, a change in the current from the power source may be dominant as noise radiated from the antenna of the power source line. In many case, the package or measurement system as well as the power source is also problematic.
For example, in recent years, the EMI noise in the LSI has become an important problem so that the method of measuring the EMI noise in the LSI is being standardized by the IEC (International Electric Standard Committee). Analysis techniques such as magnetic probe technique or VDE technique have been proposed. Thus, LSI vendors can appeal the EMI noise performance of their own LSI for customers. The customers also can absolutely compare the LSIs from the standpoint of the EMI noise. Further, if the standard measuring technique prevails, the standard of the EMI noise of the LSI will be established.
However, conventionally, since the measurement system (measuring device and printed board for measurement) has not be taken into consideration, in the stage of developing the LSI, whether or not the LSI satisfies the above standard could not be determined.
Further, with respect to a signal, although there is a case where “ringing overshoot” occurring when the signal changes is problematic, in many cases, the fact that a change in a power source level within the LSI conducts as a signal waveform is problematic. It seems that the noise which conducts or radiates in either passage of the power source or signal is strongly correlated with a change in the power source current.
An explanation will be given of a power source current for a CMOS circuit using a simple inverter circuit. When an input voltage to the inverter varies, a load capacitor charging/discharging current which is a main power source current flows. A tunneling current also flows additively. Where such a CMOS circuit is designed, synchronization is carried out because of limitation of using an automated designing tool. However, owing to the synchronization, the circuits in the entire LSI operate simultaneously, and hence a peak current in the power source is generated in synchronism with a reference clock. In addition, in order to realize the high speed or shorten the period, the transistor size is increased to implement the charging/discharging in a short time. This increases the peak current. As a matter of course, large-scaling of the LSI increases the power source current in the entire LSI. In this way, the peak current of the power source increases and the power source current varies abruptly. This abrupt variation increases a harmonic component and leads to an increase in the EMI.
To execute accurate simulation of the variation in the power source current which may be a main cause of the EMI is efficient as evaluation of the EMI in the LSI.
Meanwhile, conventionally, the current simulation technique of conducting a current analysis in a transistor level has been used.
FIG. 46
is a block diagram showing a processing flow of a conventional EMI analyzing method using the current analysis technique in a transistor level. This method includes steps of layout parameter extraction (hereinafter referred to as LPE)
4603
from the layout information of an LSI which is an analysis object; circuit simulation
4606
about a switch level netlist; current source modeling processing
4608
; power source line LPE processing
4610
; transient analysis simulation
4612
; and FET processing.
Referring to
FIG. 46
, an explanation will be given of the respective steps.
In step
4603
, using inputs of: the layout data
4601
of a semiconductor integrated circuit which is an object for EMI analysis and an LPE rule
4602
which defines a transistor element or various line parasitic elements (resistor, capacitor, etc.), the parameter value of each element, and an output format of their extracted result, on the basis of the LPE rule
4602
, the parameter of each element in the layout data
4601
is computed to create a netlist
4604
. Incidentally, in this step, the parasitic element of a power source (and ground) is not used as the object of extraction.
In step
4606
, using inputs of the netlist
4604
created from the above step
4603
and a test pattern
4605
for recreating a desired logic operation in an analysis object circuit, according to the operating status of an internal circuit, a charging/discharging current for charging/discharging a load capacitance, a tunneling current, etc. are computed to create current waveform information
4607
for each transistor. Incidentally, the first processing in this step is carried out on the assumption that the power source (and ground) potential is an ideal potential with no change.
In step
4608
, an input of current waveform information
4607
for each transistor created in the previous step
4606
is modeled into a format applicable to later step
4612
to create current source element model information
4609
. Incidentally, in order to reduce the burden of processing in the later step
4712
, the technique of modeling the current source element for each functional circuit block constructed of a plurality of transistors is generally adopted.
Step
4610
Hirano Shouzou
Mizokawa Takashi
Ohhashi Tatsuo
Shimazaki Kenji
Tsujikawa Hiroyuki
Hoff Marc S.
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
Suarez Felix
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