Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-05-31
2003-07-15
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110
Reexamination Certificate
active
06594178
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application relies for priority upon Korean Patent Application No. 2001-1363, filed on Jan. 10, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to flash memory devices electrically capable of erasing and programming, and more particularly to a method for optimizing the distribution profile of cell threshold voltage erased in a NAND-type flash memory device.
2. Description of the Prior Art
Flash memory devices have an excellent data storage capacitance as one kind of non-volatile devices which erase and program data using a tunneling phenomenon. In addition, the devices have not only lower power consumption than that of hard disk but also exhibit excellent durability against external impacts, which makes flash memory extremely useful in portable apparatuses as an auxiliary memory device.
There are two main types of flash memory: those based on NAND logic devices and those that are NOR-based. NAND-type flash memory devices in which a certain number of memory cells are connected in series. NOR-type flash memory devices include memory cells connected in parallel. NAND devices typically require smaller memory cells relative to NOR devices and thus are more economical for large storage capacitances.
FIG. 1
shows a schematic of a general NAND flash memory device. Referring to
FIG. 1
, the NAND flash memory device includes a memory cell array
10
divided into a plurality of blocks, page buffers
20
and
30
that detect and store input/output data of the memory cell, a row decoder
40
that selects word lines of the memory cell array
10
, and column decoders
50
and
60
that control input/output of data in the page buffers
20
and
30
. In the memory cell array
10
, a plurality of memory cells coupled serially with a single bit line BL form a string. The plurality of memory cells are divided into a unit of a page based on the memory cells coupled with a word line WL, and divided into a unit of a block B
1
through Bn formed of a plurality of the pages. A size of the block is generally dependent on the number of the strings connected to the single bit line BL. Such NAND flash memory devices perform read-out and programming operations in the unit of the page, and erasing operations in the unit of the block.
When data is read-out, a string selection transistor SST and a ground selection transistor GST are turned on to connect a memory string MS to the bit line BL. Then, a reference voltage (usually zero volts) is applied to a selected word line WL, while a read-out voltage is applied to the rest of the word lines. Here, the read-out voltage is higher than a threshold voltage of an erased or programmed memory cell, and zero V is applied to common source line CSL. As a result, it is determined whether the selected memory cell is an on-cell or an off-cell by detecting whether current flows in the corresponding memory string MS or not. If the selected memory cell is determined as the off-cell, the memory cell is in a programmed state; while if the selected memory cell is determined as the on-cell, the memory cell is in an erased state.
In an erasing operation in the unit of the block, source and drain are placed in a floating state, i.e., have no bias voltage, and then an erase voltage Ver of about 24 V is applied to bulk, as shown in the following <TABLE 1>. Further, the string selection signal SS and ground selection signal GS are respectively coupled to power supply voltage Vcc for string selection line SSL and ground selection line GSL of the entire blocks to be floated so that stresses caused from a positive high voltage applied to the bulk are relieved. Then, the word lines WL of the selected block are coupled to zero V, and the word lines WL of the unselected block are floated in order not to be erased.
TABLE 1
Selected block
Unselected block
Classification
On-cell BL
Off-cell BL
On-cell BL
Off-cell BL
BL
Floating → Ver
Floating → Ver
SSL
Floating → Ver
Floating → Ver
WL
Vss (ground voltage)
Floating → Ver
GSL
Floating → Ver
CSL
Floating → Ver
P-type/N-type
Ver (about 24 V)
bulk
After the erase operation in the unit of the block, the read-out operation for verifying the erase is carried out to detect “PASS” or “FAIL”, and the result is stored in a status register to complete the erasing operation.
The lines or regions which are floated in the erase operation are charged up to a voltage increased by capacitive coupling caused from the high-leveled erase voltage Ver applied to the bulk in accordance with the erase voltage level during the erasing operation. In other words, if the floating gate is coupled with the erased memory cell, stored charges thereof do not tunnel to the bulk regions since the unselected word lines on the floating state rise up to a predetermined potential with being capacitive coupled with the erase voltage applied to the bulk.
In the program operation in the unit of the page, zero V is applied to the bit line BL of the memory cell to be programmed, and a high-leveled program voltage Vpgm is applied to the corresponding word line WL. Then, the threshold voltage is increased by tunneling electrons from a channel (or bulk) to a floating gate. This is shown in the following <TABLE 2> that shows a voltage bias status when memory cell M
13
is selected for the program operation.
TABLE 2
Selected block
Unselected block
Classification
On-cell BL
Off-cell BL
On-cell BL
Off-cell BL
BL
0 V
Vcc
0 V
Vcc
SSL
Vcc
0 V
Unselected
Vpass(7~10 V)
Floating
WL15
Unselected
0 V
Floating
WL14
Selected WL13
Vpgm (14~20 V)
Floating
Unselected
0 V
Floating
WL12
Unselected
Vpass
Floating
WL11~WL0
GSL
0 V
Floating
CSL
Vss
P-type/N-type
0 V
bulk
There are memory cells that are to be programmed (program cell) as well as other memory cells that are intended to be prevented from programming (program-inhibit cell) within a single page. For the purpose of preventing such undesirable programming, channel voltage is self-boosting due to the capacitive coupling between the gate and the channel. As a result, the voltage difference between the gate and the channel is so small such that the electrons do not tunnel to the floating gate, thereby preventing the programming operation. Boosting loss caused from charge sharing is suppressed by applying zero V to word lines WL
12
and WL
14
adjacent to the selected word line WL
13
. This improves the efficiency of the device by preventing the undesirable programming through self-boosting. Such an operating manner is called local self-boosting.
In the program process, if threshold voltage profile of the erased memory cells is wide, the self-boosting efficiency is degraded by leakage current. In particular, since over-erased memory cells distributed on the lowest region of the threshold voltage profile are programmed faster than the other memory cells, these cells are easy to be over-programmed after the program operation.
In
FIG. 2A
, memory cell M
12
oe
is over-erased (i.e. a threshold voltage of a memory cell disposed in lower part in a string has much lower value than that of the memory cell which has program stress in upper part) assuming that memory cell M
13
pd
, positioned in the same word line with the selected memory cell M
13
, receives stress during the program). If so, there is the leakage current flowing in the direction of the dotted arrows until the channel voltage of the memory cell M
13
pd
is boosted up to more than an absolute value (6V) of the threshold voltage (about −6V; an over-erased state) of the memory cell M
12
oe.
As shown in
FIG. 2B
, the leakage current causes the boosted channel voltage Vch
1
(about 9V) to fall down to Vch
2
(about 6V). The memory cell M
13
pd
thence receives the program stress and the program-inhibit is extinguished. Memory cell M
13
pi
, on normally erased memory cell M
12
ne
having a threshold voltage of about −3V, does not have leakage current be
Choi Sun-Mi
Lee Yeong-Taek
Elms Richard
Marger Johnson & McCoolom, P.C.
Phung Anh
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