Method for optimizing contact pin placement in an integrated cir

Details Method for optimizing contact pin placement in an integrated cir Method for optimizing contact pin placement in an integrated cir

1997-05-01

2000-06-13

Teska, Kevin J.

39550003, 39550015, G06F 1750

Patent

active

060759348

ABSTRACT:
A method for optimizing contact pin placement in an integrated circuit, wherein a netlist containing connectivity information, and placement information for a semiconductor circuit is read. Each net in the circuit is classified (510). Unblocked tracks are identified for each net in the circuit (512). All contact pins associated with nets having a power supply classification are placed according to a power supply location (513). The blockage for each remaining net is updated. Next, all contact pins for nets residing within a defined diffusion are placed (514) The blockage for each remaining net is updated. Next, all contact pins for nets residing in multiple defined diffusion areas are placed (515).

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