Boots – shoes – and leggings
Patent
1990-10-29
1993-05-04
Trans, Vincent N.
Boots, shoes, and leggings
364490, 364489, 364488, G06F 1560
Patent
active
052087646
ABSTRACT:
A computer integrated circuit arrangement including flip-flop circuits, buffers, and combinatorial circuit elements in which the flip-flop circuits are arranged in rows with buffers which may be connected to drive signals to those flip-flop circuits, the flip-flop circuits having conductors designed to carry global signals arranged to traverse the width of the flip-flop circuits and provide input and output terminals to match input and output terminals of adjacent flip-flop circuits.
REFERENCES:
patent: 4683384 (1987-07-01), Shibata et al.
patent: 4805113 (1989-02-01), Ishii et al.
patent: 4942317 (1990-07-01), Tanaka et al.
patent: 5029279 (1991-07-01), Sasaki et al.
"Standard Cell VLSI Design: A Tutorial" by Kessler et al., IEEE Circuits and Devices Magazine, Jan. 1985, pp. 17-34.
"Theory and Concept of Circuit Layout" by Hu et al., IEEE 1985, pp. 3-18.
"CAD System for IC Design" by Daniel et al; IEEE Trans on Computer-Aided Design, vol. CAD-1, No. 1, Jan. 1982, pp. 2-12.
"Automatic Generation of Digital System Schematic Diagrams" by Arya et al., IEEE 22nd Design Automation Conf., 1985, pp. 388-395.
Rusu Stefan
Yang Joseph S.
Sun Microsystems Inc.
Trans Vincent N.
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