Method for optimization of multi-level interconnect RC delay

Details Method for optimization of multi-level interconnect RC delay Method for optimization of multi-level interconnect RC delay

1996-11-12

1999-06-08

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Diverging with single input and plural outputs

327416, H03K 1762

Patent

active

059107472

ABSTRACT:
A method is herein provided for placing drivers and repeaters along the interconnect so as to optimize interconnection propagation delay with respect to area and time constraints. The method provided optimizes the propagation delay and simplifies the propagation delay determination by first using drivers to divide an interconnect into forkless branches, then linearizing the delay of each branch by placing repeaters along the length of the branches.

REFERENCES:
patent: 5614844 (1997-03-01), Sasaki et al.
Bakoglu, H.B. & J.D. Meindl, "Optimal Interconnection Circuits for VLSI," IEEE Trans. On Electron Devices, vol. ED-32, No. 5, May 1985, pp. 903-909.

Affiliated with

Also associated with

Rating

Method for optimization of multi-level interconnect RC delay does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for optimization of multi-level interconnect RC delay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for optimization of multi-level interconnect RC delay will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1685315