Boots – shoes – and leggings
Patent
1992-05-04
1994-10-25
Black, Thomas G.
Boots, shoes, and leggings
307590, 364569, 364577, 364578, 371 23, G06F 1516
Patent
active
053595351
ABSTRACT:
A method for optimization of delay times in a digital circuit. The method comprises selecting a logic gate (12), and constructing a model (35) which predicts the delay time (27) of the logic gate (12). Varying the parameters which control the model to more accurately predict the delay time (48). Summing the delay time (48) due to each logic gate (12) which comprises the signal path. Repeating the method for each signal path within the digital circuit until all signal paths are computed. Modifying the digital circuit based on the calculated delay times (48) so as to better satisfy a predetermined measurement criteria.
REFERENCES:
patent: 4263651 (1981-04-01), Donath et al.
patent: 4698760 (1987-10-01), Lembach et al.
patent: 4907180 (1990-03-01), Smith
patent: 4970664 (1990-11-01), Kaiser et al.
patent: 5051911 (1991-09-01), Kimura et al.
patent: 5105374 (1992-04-01), Yoshida
patent: 5206889 (1993-04-01), Unkrich
patent: 5239481 (1993-08-01), Brooks et al.
patent: 5245543 (1993-09-01), Smayling et al.
patent: 5274568 (1993-12-01), Blinne et al.
O'Brien et al., "Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation", IEEE, 1989, pp. 512-515.
Patel, Dhimant, "CHARMS: Characterization and Modeling System for Accurate Delay Prediction of ASIC Designs", IEEE 1990 Custom Integrated Circuits Conference, pp. 9.5.1-9.5.6.
Djaja Gregory
Jennings Timothy J.
Schucker Douglas W.
Shapiro Frederic B.
Black Thomas G.
Garbowski Leigh Marie
Motorola Inc.
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