Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
1998-08-04
2004-10-05
Patel, Gautam R. (Department: 2655)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S220000
Reexamination Certificate
active
06801995
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method of encoding instructions for a processor to realize the maximum number of encoded instructions.
BACKGROUND OF THE INVENTION
One aspect of designing processors, such as digital signal processors, is selection of the particular instructions to be encoded from the entire set of instructions which is supported by the hardware. In a typical selection process, instructions are grouped according to the type of function performed, i.e., multiply accumulates, barrel shifts, etc. For each group, a certain number of instruction bits are set aside to be used to identify the registers affected by the instruction.
For example, in a processor with 16 general purpose registers, four bits are required to identify each register. A particular type of command function that can be executed using either one or two registers will conventionally have eight bits in the instruction op-code reserved to identify the registers. Commands in this group which utilize only a single register use only four of the reserved eight bits. In these commands, the four other bits are unused and are therefore wasted.
SUMMARY OF THE INVENTION
According to the invention, instructions for a computer processor are encoded to minimize the number of wasted bits and maximize the number of encoded instructions. Rather than group instructions according to function, they are arranged in “resource groups” according to the resources used by the instruction. All instructions in a particular resource group therefore require the same number of available bits in order to identify the designated resources, regardless of the particular function performed. In a particular example, the designated resources are the classes and number of registers used by a particular instruction.
In a preferred embodiment, instructions are encoded so that the highest order active bits identify the resource grouping of the instruction. The remaining low order bits are then available to encode a given number of instructions from the specific group. This encoding scheme eliminates wasted bits in instructions and thereby increases the number of instructions which can be implemented.
Increasing the size of the instruction space in this manner allows the formation of an orthogonal instruction set and the definition of special purpose instructions for specific applications. An increase in functionality per instruction also leads to performance improvements. In addition, encoding instructions in this manner can reduce the amount of decoding logic required, because once the resource group for a particular instruction is identified, connections to the specifically identified resources can be established independently of the determination of the specific function of the instruction.
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Alidina Mazhar M.
Simanapalli Sivanand
Thierbach Mark E.
Agere Systems Inc.
Patel Gautam R.
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