Method for operation of a bus system for highly flexible and qui

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395309, G06F 1300

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active

058288520

ABSTRACT:
A method and a circuit configuration for operation of a bus system. A bus includes a bus control unit which controls only an arbitration and when time is exceeded during a data transmission. An actual data transmission is determined in a respective active master unit and an addressed slave unit. A characteristic of a bus cycle, such as a data length, access to a data area or a control area and a waiting cycle, is transmitted in encoded form through a multiplicity of control lines.

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IBM Technical Discl. Bulletin vol.28 No. 12 May 1986, pp. 5329-5333, "High-Speed Processor Bus Arbitration".
Elektronik Report 10A Oct. 1990, pp. 58-62, "Vorstellung des MC68340" (Introduction of the MC68340), in German.
Faer, Gerog. Bussysteme-Parallele und Serieele Bussysteme, Lokale Netze. pp. 46-48. R. Oldenburg Verlag, 1987. (filed in German).

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