Method for operating nonvolatile memory cells

Details Method for operating nonvolatile memory cells Method for operating nonvolatile memory cells

2000-05-31

2002-12-10

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185290, C365S185330, C365S185180, C365S185260

Reexamination Certificate

active

06493262

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices and methods for operating such devices; and more particularly the present invention addresses the method and conditions of erasing nonvolatile memory cells, with special emphasis on triple-polysilicon source-side injection flash EEPROM (electrically erasable and programmable read-only-memory) cells.
2. Description of Related Art
A flash memory cell relies on a floating-gate to store electrical charges. The amount and the polarity of these charges affect the ability of the underlying channel to conduct electrical current. Flash memory cells as known today are constructed either in the form of a four-terminal device (with drain, control-gate, source, and substrate), which is typically made using a double-polysilicon process; or in the form of a five-terminal device (with drain, control-gate, select-gate, source, and substrate), which is typically made using a triple-polysilicon process. In either form, the floating-gate is situated between the control-gate and the substrate.
FIG. 1A
is a cross-sectional view of a typical four-terminal, drain-side injection cell
10
. The cell
10
includes a P-type substrate
12
, N+ source
14
, control-gate
16
, floating-gate
18
, and N+ drain
20
. The erase action in this cell takes place at source region
14
, which may be a singly or doubly diffused junction as indicated.
FIG. 1B
is the erase-mode biasing condition of the memory cell
10
, which involves two erase signals, namely, the positive source voltage (Vs)
22
and the negative control-gate (Vcg)
24
.
FIG. 2A
is a cross-sectional view of a five-terminal flash memory cell
30
. Cell
30
includes P-type substrate
32
, N+ source
34
, sidewall gate
36
, control-gate
38
, floating-gate
40
, and N+ drain
42
.
FIG. 2B
is the erase-mode biasing condition of the cell
30
, which also involves two erase signals, namely, the negative control-gate voltage (Vcg)
44
and positive drain voltage (Vd)
46
.
FIG. 3A
shows a typical source-side injection cell
60
which includes a P-type silicon substrate
62
, a pair of heavily doped N-type source and drain regions
64
,
72
, and three polysilicon (poly) layers surrounded by insulating dielectric. The first polysilicon layer comprises the floating-gate
70
, on which charge is stored, while the second polysilicon layer comprises the control-gate
68
. As is characteristic of all source-side injection cells, the cell also incorporates a select-gate
66
which is made of a third poly layer which overlaps or extends over the source
64
, a portion of the channel region
74
, control-gate
68
, and drain
72
. In the operation of such memory cell
60
, the source
64
, drain
72
, control-gate
68
, and select-gate
66
are each connected to voltage supplies, while the substrate terminal
62
is tied to ground. The cell channel
74
, defined on the substrate surface
62
between the source and drain terminals
64
,
72
, is split into two serial sections, with one section connecting to the drain
72
and lying under the floating-gate
70
, and the other section connecting to the source
64
and lying under the select-gate
66
. With an applied drain-to-source voltage, the channel current is controlled by the voltages at: (1) the floating-gate
70
, and (2) the select-gate
66
. To conduct current, the voltages at the floating-gate
70
and the select-gate
66
need to be positive; to shut off current requires only a voltage at or below the ground potential appear on either the floating-gate
70
or the select-gate
66
.
FIG. 3B
is a cross-sectional view of another five-terminal cell
80
. The cell
80
includes a P-type substrate
82
, N+ source
84
, select-gate
86
, control-gate
88
, floating-gate
90
, and N+ drain
92
. The select-gate
86
extends over a portion of the channel region
74
, and only partially overlaps or extends over control-gate
88
, whereas select-gate
66
of
FIG. 3A
completely overlaps source
64
, control-gate
68
and drain
72
. The source-side injection cell
80
of
FIG. 3B
is functionally equivalent to that of FIG.
3
A.
FIG. 3C
is the erase-mode biasing condition of the cell
80
. Of the two involved erase signals, the positive voltage (Vd)
94
is on the drain
92
and the negative voltage (Vcg)
96
is on the control-gate
88
. Note that exact same erase condition can be applied to the cell
60
of FIG.
3
A.
Source-side injection cells as set forth by Y. Ma et al., for triple-polysilicon flash memory arrays (U.S. Pat. Nos. 5,280,446 and 5,278,439) have two basic advantages over the conventional four-terminal (a.k.a. “drain-side injection”) cells: (1) in write-mode, source-side injection cells provide superior programming efficiency in terms of reduction of the required channel current, and (2) in erase-mode, the requisite split-gate eliminates the so-called “over erase” condition, thus avoiding a problematic issue which the non-split-gate cell must confront. Based on triple-polysilicon technology, the patent of Fukumoto (U.S. Pat. No. 5,394,360) describes various implementations of the source-side injection memory cell.
Applications of flash memory cells involve three basic operation modes: write, erase, and read. To write a cell means to inject negative charges onto the floating-gate. To erase a cell means to remove the negative charges from the floating-gate, or to displace the negative charges with positive charges. To read a cell means to detect the state of the floating-gate's stored charges by sensing the current flowing through the drain-to-source channel located underneath the floating-gate, thereby resulting in binary logic states or in multi-level logic states.
Fowler-Nordheim tunneling is the dominant erase mechanism for transporting electrical charges from the floating-gate to the substrate. The patent of Haddad et al. (U.S. Pat. No. 5,077,691) teaches a method using a very large negative control-gate voltage (e.g., −12 V to −17 V) combined with a low positive source voltage (e.g., +0.5 V to +5.0 V) for erasing a four-terminal cell. During erase, the charge transfer occurs at the overlapped capacitor between the floating-gate and the source junction. The patent of Caywood (U.S. Pat. No. 5,235,544) teaches: a method using similar conditions (e.g., Vcg=−11 V and Vd=+5 V) for erasing a five-terminal cell, however the select-gate terminal is inactive or left floating. The charge transfer in this case occurs at the overlapped capacitor between the floating-gate and the drain junction. Common to both cases, there are two signals involved in the cell erase: one is negative, one positive; and the substrate (the body-terminal) is kept at ground potential. The relatively low positive erase signal is taken directly, without charge pumping, from the “standard 5 V power-supply voltage.” The negative erase signal for the control-gate, however, requires intensive charge pumping in order to support a strong electric field for the electrons to tunnel. As addressed below, the resulting “magnitude disparity” between the required negative and positive voltages is not a favorable condition for advanced technologies. More specifically, the magnitude disparity results in voltage stresses concentrated on one of the cell dielectrics.
Advanced memory chips, containing higher memory density and smaller transistors, demand that the power-supply voltage be reduced below the “old 5 V standard” levels. Indeed, modern power-supplies are re-standardized to such voltages as 3.3 V, 2.5 V, or 1.8 V. For the low power-supply voltage cases, voltage pumping is now required for both positive as well as negative polarities in order to satisfy the erase conditions. In this case, the magnitude disparity between the negative and positive voltages becomes very undesirable for three reasons: (1) voltage pumping from a low level (e.g., 3.3 V) supply-voltage is more difficult than from the “old 5 V standard” power suppl

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