Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-01-11
2005-01-11
Flynn, Nathan J (Department: 2826)
Static information storage and retrieval
Floating gate
Particular biasing
C257S314000, C257S315000
Reexamination Certificate
active
06842374
ABSTRACT:
An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second N-type doped region is laterally disposed in the P-type substrate. The second N-type doped region is also adjacent to the first gate. A second gate, which acts as a select gate or select gate of the EEPLD, overlies the P-type substrate and is adjacent to the second N-type doped region. A third N-type doped region is disposed in the P-type substrate. The third N-type doped region is adjacent to the second gate. By Applying a sufficient voltage on the first N-type doped region (VBL), and changing a select gate voltage (VSG) or the third N-type doped region voltage (VSL) applied on the second gate of the EEPLD, the operation of the EEPLD can be selectively implemented either under a channel hot hole (CHH) program mode or a channel hot electron (CHE) erase mode.
REFERENCES:
patent: 5952700 (1999-09-01), Yoon
patent: 6015977 (2000-01-01), Zahorik
patent: 6414872 (2002-07-01), Bergemont et al.
patent: 6570212 (2003-05-01), Mehta et al.
Ho Ming-Chou
Hsu Ching-Hsiang
King Ya-Chin
Lee Kung-Hong
Shen Shih-Jye
e-Memory Technology, Inc.
Flynn Nathan J
Quinto Kevin
Winston Hsu
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