Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-07-28
2001-04-03
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185140, C365S185240, C365S185300
Reexamination Certificate
active
06212103
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an electrically erasable programmable floating gate memory, such as flash memory or electrically erasable programmable read only memory (EEPROM) for both memory and programmable logic application. More specifically, the present invention relates to a method to implement high density and high speed flash memory with a single low voltage power supply.
BACKGROUND OF THE INVENTION
FIG. 1
is a schematic diagram of an array
100
of conventional flash memory cells (flash cells) detailed in U.S. Pat. Nos. 5,357,465 and 5,222,040. Array
100
includes flash cells
110
-
113
, word lines
101
-
102
, common source line
103
, and drain bit lines
105
-
106
, as illustrated.
In general, a non-volatile flash memory transistor (e.g., flash cell
110
) includes a floating gate that can be programmed to store either a negative charge or a neutral charge. The amount of charge stored on the floating gate affects the threshold voltage of the flash cell. The threshold voltage of a flash cell is that voltage at which the flash memory transistor turns on, allowing full current to flow. When storing a negative charge, a flash cell is said to be in an erased state. When storing a neutral charge, a flash cell is said to be in a programmed state. When a flash cell is in the erased state, the negative charge stored on the floating gate prevents the flash cell from turning on at the low voltages used for reading the flash cell during a read operation. Therefore the erased flash cell is said to be in a high threshold state. When a flash cell is in the programmed state, the neutral charge stored on the floating gate allows the flash cell to be controlled by the voltage applied to the control gate of the flash cell. Therefore the programmed flash cell is said to be in a low threshold state.
FIG. 2
is a cross-sectional view of flash cell
110
of array
100
. Flash cell
110
includes p-substrate
160
, n-well
170
, n-well contact
171
, p-well
180
, p-well contact
181
, source
120
, drain
130
, tunnel oxide region
153
, floating gate
154
, isolation material
155
, and control gate
156
. Control gate
156
is conventionally word line
101
, thereby coupling flash cell
110
to other flash cells in the array. The entire array of flash cells is fabricated within p-well
180
, n-well
170
, and substrate
160
. The charge on floating gate
154
determines the threshold voltage of and identifies the state of flash cell
110
.
FIG. 3
is a table describing the voltages for operating array
100
. Array
100
can perform program, program inhibit erase, and read operations, as illustrated.
During the program mode, relatively high voltages are applied across the control gate (0 Volt) and the drain (+5 Volts) of flash cells on the non-selected word line and the selected drain bit line. These high voltages can result in drain disturb in erased cells. Drain disturb occurs when an electrical field is strong enough to cause the floating gate to experience a charge loss due to electron tunneling from the floating gate to the drain. It is therefore an object of the present invention to lessen the drain disturb in a flash array.
Minute variations in the size of the elements of a transistor can occur during transistor formation. As a result, some flash cells can have slightly thinner or thicker tunnel oxide regions. Electrons tunnel more easily through flash cells having thinner tunnel oxide regions during a program operation. As a result, flash cells having a thinner tunnel oxide region are less negatively charged during a program operation. These flash cells therefore have a lower threshold voltage than flash cells with thicker tunnel oxide regions. In some cases, the floating gate of a flash cell can lose enough charge to cause the threshold voltage of the flash cell to go negative. When this happens, a grounding voltage applied to the control gate does not turn off the flash cell. Cells with negative threshold voltages are called over-programmed cells. To conventionally prevent non-selected cells from turning on, a voltage more negative than the negative threshold voltage of the most over-programmed cell must be applied to each non-selected cell in the array. This large negative voltage causes a large voltage to be applied across the control gates and the drains of the non-selected flash cells in the array. This voltage can disturb the amount of charge on the floating gate of these flash cells under certain conditions. It is therefore another objective of the present invention to find a better way to prevent turn-on of non-selected, over-programmed cells.
A flash cell is erased by applying the voltages listed in
FIG. 3
to the array for a given period of time. Erasing is performed in blanket mode, meaning that all cells in an array are erased simultaneously. An array of cells is erased by applying a large positive voltage (e.g., 20.0 Volts) to each control gate, and grounding each source, drain, and substrate. Under these conditions, electrons tunnel from the substrate to the floating gate. As a result, after erasing, all cells should be in a high threshold voltage state.
A row of flash cells is read by applying the voltages listed in
FIG. 3
to the array for a given period of time.
The junction of the drain region and a well region of a flash cell is called a drain junction. For example, the drain junction of flash cell
100
is located between the drain region (e.g., drain
130
) and the p-well (e.g., p-well
180
). The drain junction of a flash cell is designed to provide efficient F-N tunneling between the floating gate and the drain during a program operation. This is accomplished by implanting a more heavily doped (e.g., N+) region that is under-lapping the floating gate. As a result of the under-lapping, a tunneling region is created. Due to this sensitivity, applying a positive voltage to the drain may cause F-N tunneling induced read disturb in non-selected erased cells in the array. Read disturb occurs when the charge on a floating gate is altered by a read operation. In this case, read disturb occurs when an electrical field is strong enough to cause the floating gate to experience a charge loss due to electron tunneling from the floating gate to the drain. The floating gate is therefore less negatively charged after the read operation, and thus the threshold voltage of the cell is lowered. It is therefore an object of the present invention to lessen the read disturb occurring to non-selected, erased cells.
As an additional result of the under-lap of the heavily doped region with the floating gate, applying a positive voltage to the drain also causes hot electron induced read disturb if the selected cell is in a programmed state. In this case, the read disturb occurs when an electrical field is strong enough to cause the electrons flowing between the source and the drain during the read operation to gain enough energy to jump through the tunnel oxide layer into the floating gate. As a result, the floating gate contains additional charge after the occurrence of the read disturb. It is therefore another object of the present invention to lessen the read disturb that can occur in selected, programmed cells during a read operation.
Each cell in array
100
(
FIG. 1
) has one metal line and one diffusion line. Drain bit lines
105
and
106
are metal bit lines, and common source line
103
is a diffusion line. Diffusion lines inherently have large leakage current as well as large resistance and capacitance delays. As a result, the conduction performance of diffusion lines essentially act as an efficient connector coupled to a resistor and a capacitor. The added resistance and capacitance on the line is called RC delay. The RC delay of the diffusion line delays current along the line, thus delaying accesses to memory array
100
. It is therefore another object of the present invention to increase the access speed to a flash memory array.
FIG. 4
is a layout diagram containing flash memory array
100
. Similar elements in
FIGS. 1
,
2
Ahrens Michael G.
Dejenfelt Anders T.
Lin Qi
Olah Robert A.
Bever Hoffman & Harms LLP
Cartier Lois D.
Le Vu A.
Nguyen Hien
Stephenson Julie A.
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