Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-11-20
2003-11-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185010, C365S185180, C365S185240, C365S185260, C365S185280
Reexamination Certificate
active
06643170
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90126237, filed on Oct. 24, 2001.
BACK GROUNDING OF THE INVENTION
1. Field of Invention
The present invention relates to a method for operating a multi-level memory. More particularly, the present invention relates to a method for operating a silicon nitride read-only memory (NROM).
2. Description of Related Art
The threshold voltage characteristic of an erasable and programmable read-only memory (EPROM), an electrical erasable and programmable read-only memory (EEPROM) and a flash memory is controlled by the total charges that are retained in the floating gate. A memory cell uses different threshold voltage ranges to define the various threshold voltage levels. Every level of the threshold voltage defines a different memory state of a multi-level memory cell.
FIG. 1
is a cross-sectional view showing the memory cell of a flash memory device according to the prior art. As shown in
FIG. 1
, a gate structure
102
includes, sequentially from bottom to top, an oxide layer
108
, a polysilicon layer as the floating gate
104
, an oxide layer
110
, a nitride layer
112
, an oxide layer
114
and a polysilicon layer as the control gate
106
. The floating gate
104
is in a “floating state”, which is not connected with any line and is used for charge storage. The control gate
106
controls the storage and retrieval of information. The formation of the gate structure
102
thus requires a multiple of masking processes. Moreover, an additional voltage is applied to the control gate during the programming of the flash memory device
100
to provide the bias that is required for the programming of the flash memory device
100
.
The aforementioned flash memory
100
(as shown in
FIG. 1
) typically can store a single bit of data, for example, a logic “0” state or a logic “1” state.
FIG. 2
is a diagram illustrating the method for detecting the logic “0” state or the logic “1” state by a memory cell. During a reading operation, a voltage V
read
is applied to the gate. If the voltage V
read
is smaller than the threshold voltage Vt, no current would travel through the source region and the drain region of the memory cell, and a logic state of “0” is determined. If the voltage V
read
is greater than the threshold voltage Vt, a large current would travel through the source region and the drain region of the memory cell to determine a logic state of “1”.
The development of the high-density flash memory cell provides four memory states in a single bit of memory.
FIG. 4
illustrates the distribution of the three threshold voltages (Vt
1
, Vt
2
, Vt
3
) of a memory cell of a high density flash memory device. Similar to the conventional memory that stores a single bit of memory, a voltage V
read
is applied to the gate during the reading of a memory cell. If V
read
is less than Vt
1
, a current is traveled through the source region and the drain region of the memory device to determine a logic state of “00”. If V
read
is greater than Vt
1
but is less than Vt
2
, as in
FIG. 3
, a higher current would travel through the source region and the drain region of the memory cell to determine a logic state of “01”. The logic state of “10” is determined if the V
read
voltage is between the threshold voltage Vt
2
and Vt
3
and the logic state “11” is determined if the V
read
voltage is higher than Vt
3
, respectively.
Referring again to
FIG. 1
, an additional voltage is applied to the control gate during the programming of the flash memory device
100
to provide the bias that is required for the programming of the flash memory device
100
. In order to reduce the bias that is required for the programming of the flash memory device
100
, an additional polysilicon layer is formed between the oxide layer
108
and the floating gate
104
to increase the coupling ratio of the floating gate
104
and to reduce the required bias during the programming of the flash memory device
100
. An additional ion implantation process (as illustrated by the slanted line region
120
in
FIG. 1
) may also performed in the regions near the source region
118
and the drain region
116
, respectively. The additional ion implantation would increase the erasure capability of the flash memory device
100
. The additional implantation process, however, would complicate the semiconductor processing and increase the production cost.
SUMMARY OF THE INVENTION
The present invention provides a method for programming a multi-level memory cell. When a NROM structure is used to fabricate the multi-level memory cell, it only requires fixing the bias and reading one side of a bit. The fabricating method of the present invention to form a multi-level memory cell is to simplify the semiconductor processing so that, the production cost is reduced.
The present invention provides a method for programming a multi-level NROM cell. The multi-level NROM cell comprises a silicon nitride layer, wherein the silicon nitride layer can locally trap a plurality of charges to form a plurality of charge trapping regions. The charges stored in these charge-trapping regions are the first bit of memory and a second bit of memory, respectively. The charges that are stored in the trapping region as the second bit of memory form an electrical barrier. The level of the threshold current depends on the size of the electrical barrier. The different levels of the threshold currents are thereby used to define the different memory states of the multi-level NROM memory cell.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6269023 (2001-07-01), Derhacobian et al.
patent: 6320786 (2001-11-01), Change et al.
patent: 6396741 (2002-05-01), Bloom et al.
Chou Ming-Hung
Huang Jen-Ren
J. C. Patents
Macronix International Co. Ltd.
Yoha Connie C.
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