Method for operating a memory array

Details Method for operating a memory array Method for operating a memory array

1996-02-20

1998-01-06

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

36518502, 36518524, G11C 1140

Patent

active

057062285

ABSTRACT:
A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.

REFERENCES:
patent: 4961002 (1990-10-01), Tam et al.
patent: 5047981 (1991-09-01), Gill et al.
patent: 5191556 (1993-03-01), Radjy
patent: 5267209 (1993-11-01), Yoshida
patent: 5408431 (1995-04-01), Challa
patent: 5471422 (1995-11-01), Chang et al.

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