Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2003-03-07
2004-07-13
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S065000
Reexamination Certificate
active
06762628
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for operating a comparator and a pre-amplifier of an integrated circuit, which pre-amplifier is connected in series to the comparator, according to the precharacterising part of claim 1, as well as to an integrated circuit arrangement comprising a comparator and a pre-amplifier which is connected in series to the comparator, according to the precharacterising part of claim 9.
2. Description of the Prior Art
Such a method and such a circuit arrangement is for example known from “Razavi et al, IEEE Journal of Solid-state Circuits, vol. 27, no. 12, December 1992, pp. 1916-1926”. FIG. 1 of said article diagrammatically shows a comparator with a pre-amplifier connected in series. FIGS. 5 and 6 of said article show embodiments of a pre-amplifier which can be operated with clock pulses, and of a comparator (latch) which can be operated with clock pulses. By means of suitably selected periodical clock pulse signals for controlling the pre-amplifier and the comparator, this arrangement makes it possible, at periodical decision points, to compare the signals which are present at the input of the arrangement.
From “Nagaraj et al, IEEE Journal of Solid-state Circuits, vol. 35, no. 12, December 2000, pp. 1760-1768”, a similar circuit arrangement is known. FIG. 6 of said article shows the arrangement in an ADC, wherein two pre-amplifier stages are connected in series to individual comparators (latches). FIGS. 8 and 11 of this article show the design of the first pre-amplifier stage and the periodical signal gradients of the pre-amplifier stages which are operated with clock pulses.
From “David Johns, Ken Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997, pp. 316-331 (compare FIG. 7.13 of said article), it is know to connect a pre-amplifier in series to a comparator.
FIG. 1
shows an arrangement, designed in the known way, comprising a comparator
10
and a pre-amplifier
20
which has been connected in series to the comparator
10
so as to improve the resolution. As is also shown in
FIG. 1
, it is also possible to connect several pre-amplifiers in series to the comparator
10
.
By being controlled with a periodical clock pulse signal CLK, the comparator
10
is operated so as to compare comparator input signals at periodical decision points, wherein said comparator input signals are provided to the comparator
10
by the pre-amplifier
20
in the form of output signals OUT+ and OUT−. At its output, the comparator
10
provides a comparator output signal which corresponds to the comparison result, namely a binary signal COUT and a signal COUT* which is inverse to the former. The pre-amplifier
20
(or the multiple number of pre-amplifiers) is/are operated by being controlled with a further periodical clock pulse signal (RST) (reset signal) so as, in amplification phases which precede the decision points, to amplify a signal which has been input to the pre-amplifier (in this instance the difference between two signals IN+ and IN−) and to provide the amplified signal as a comparator input signal (difference between signals OUT+ and OUT−), and so as, in reset phases which precede the amplification phases, to reset amplification to a minimum value (reset). This reset function prevents hysteresis effects as well as dependence of the output signals OUT+, OUT− on the past history of these signals in preceding clock pulse cycles. Preferably, the minimum value of amplification is significantly less than 1.
FIG. 2
shows an exemplary embodiment of the pre-amplifier
20
. A pre-amplifier designed in this way is for example known from the above-mentioned IEEE article (Nagaraj et al) and is shown in FIG. 8 of said article. The pre-amplifier comprises a transconductance stage which is formed from a differential pair of two FETs Q
1
, Q
2
, as well as a resistive load in the form of ohmic resistors R
1
, R
2
, arranged in series to the FETs Q
1
, Q
2
. As an alternative, the resistive load could for example also be formed by MOS diodes.
The differential input signals IN+, IN− are fed to the control-current terminals of the FETs Q
1
, Q
2
, so that on nodes between these FETs and the resistors R
1
, R
2
, the amplified signal is provided as the difference between two signals OUT+, OUT−, wherein, as is well known, amplification is greater the greater the transconductance in the transconductance stage, and the greater the resistive load.
A time constant (RC constant) is decisive for the dynamic behaviour of the pre-amplifier
20
, with said time constant being the product from resistive load and capacities. Such capacities, above all parasitic capacities, are unavoidable at the output of the pre-amplifier
20
itself and as a result of the input capacity of the subsequent stage (comparator or further pre-amplifier).
The reset function of the pre-amplifier
20
, which is clock pulsed with the reset signal RST, takes place by means of a further FET Q
3
, which is arranged between pre-amplifier output lines which are intended for providing the amplified signal, with said further FET Q
3
being operated as a switch, in that the binary reset signal RST is fed to the control-current terminal of said FET Q
3
. During a reset phase the FET Q
3
is switched on so that the pre-amplifier output lines are short-circuited by way of a relatively small source-drain resistor. As a result of this, amplification is reset to a minimum value (approaching zero), while the time constant also becomes small, so that consequently the output signal OUT+−OUT− quickly drops to values near zero. This reset function prevents hysteresis effects and during the reset phase clears any signal excursion which may still be present at the output so that in the next clock pulse cycle the output signal does not depend on the past history.
During an amplification phase which immediately follows the reset phase, the output signal of the pre-amplifier
20
should follow the input signal (which is variable in time). At the end of the amplification phase, i.e. at the decision point of the comparator
10
, the output signal has to be at least on the same side of the decision threshold as the input signal so as to ensure a reliable comparison function. In many cases of application, the characteristics of the input signal are such that, from a starting value which does not correlate to the final value, or only faintly correlates to the final value (e.g. along an exponential transient response curve), said input signal aims to reach the final value. This case occurs in particular at the output of an SC (switched-capacitor) circuit, for example in the context of quantisers in delta-sigma modulators. The case where the input signal starts with considerable excursion on one side of the decision threshold and changes to the other side only towards the end of the amplification phase constitutes the most difficult case for designing the amplifier time constant. This case is shown in FIG.
3
. The solid curve shows the gradient over time of the input signal. If the pre-amplifier
20
is designed for a short time constant and thus high speed, approximately the output signal gradient shown by a dot-dash line in
FIG. 3
results. If the pre-amplifier
20
is designed for a longer time constant and thus a lower speed, approximately the output signal gradient shown by a dashed line in
FIG. 3
results. In the first case, the final value of the output signal is on the same side as the decision threshold (dotted line), whereas in the second case, the output signal of the pre-amplifier
20
cannot follow the input signal fast enough and is still located on the other side of the decision threshold. If this second case is to be avoided, the time constant will have to be shortened. This can easily be brought about by reducing the resistive load. In practical application it is rarely possible to reduce the capacities which are decisive for the time constant. As a rule, these capacities resul
Rothwell, Figg, Ernst & Manbeck, P.C
Wells Kenneth B.
Xignal Technologies AG
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